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//**************************************************************
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// Module : virtual_jtag_addr_mask.v
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// Platform : Windows xp sp2
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// Simulator : Modelsim 6.5b
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// Synthesizer : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1
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// Targets device : Cyclone III
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Revision : 2.0
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// Date : 2012/03/12
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// Description : addr mask input from debug host via
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// Virtual JTAG.
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//**************************************************************
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`timescale 1ns/1ns
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module virtual_jtag_addr_mask(mask_out0,mask_out1,mask_out2,mask_out3,
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module virtual_jtag_addr_mask(mask_out0,mask_out1,mask_out2,mask_out3,
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mask_out4,mask_out5,mask_out6,mask_out7,
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mask_out4,mask_out5,mask_out6,mask_out7,
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mask_out8,mask_out9,mask_out10,mask_out11,
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mask_out8,mask_out9,mask_out10,mask_out11,
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mask_out12,mask_out13,mask_out14,mask_out15
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mask_out12,mask_out13,mask_out14,mask_out15
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);
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);
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