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//**************************************************************
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//**************************************************************
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// Module : up_monitor.v
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// Module : up_monitor.v
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// Platform : Windows xp sp2
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// Platform : Windows xp sp2, Ubuntu 10.04
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// Simulator : Modelsim 6.5b
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// Simulator : Modelsim 6.5b
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// Synthesizer : QuartusII 10.1 sp1
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// Synthesizer : QuartusII 10.1 sp1, PlanAhead 14.2
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// Place and Route : QuartusII 10.1 sp1
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// Place and Route : QuartusII 10.1 sp1, PlanAhead 14.2
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// Targets device : Cyclone III
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// Targets device : Cyclone III, Zynq-7000
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Author : Bibo Yang (ash_riple@hotmail.com)
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// Organization : www.opencores.org
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// Organization : www.opencores.org
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// Revision : 2.2
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// Revision : 2.3
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// Date : 2012/03/28
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// Date : 2012/11/19
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// Description : Top level glue logic to group together
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// Description : Top level: transaction record generation
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// and glue logic to group together
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// the JTAG input and output modules.
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// the JTAG input and output modules.
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//**************************************************************
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//**************************************************************
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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`include "vendor.h"
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module up_monitor (
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module up_monitor (
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input clk,
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`ifdef XILINX `ifdef AXI_IP
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input wr_en,rd_en,
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icontrol0, icontrol1, icontrol2,
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input [15:2] addr_in,
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`endif `endif
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input [31:0] data_in
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clk,
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wr_en,rd_en,
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addr_in,
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data_in
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);
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);
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input clk;
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input wr_en,rd_en;
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input [15:2] addr_in;
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input [31:0] data_in;
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Registers and wires announcment
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// Registers and wires announcment
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// for CPU bus signal buffer
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// for CPU bus signal buffer
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end
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end
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// Instantiate vendor specific JTAG functions
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// Instantiate vendor specific JTAG functions
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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`ifdef ALTERA
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// index 0, instantiate capture fifo, as output
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// index 0, instantiate capture fifo, as output
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virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
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virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
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.clk(clk),
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.clk(clk),
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.wr_in(capture_wr || pretrig_wr),
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.wr_in(capture_wr || pretrig_wr),
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.data_in(capture_in),
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.data_in(capture_in),
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.pnum_out(pretrig_num)
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.pnum_out(pretrig_num)
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);
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);
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defparam
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defparam
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u_virtual_jtag_adda_trig.trig_width = 56,
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u_virtual_jtag_adda_trig.trig_width = 56,
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u_virtual_jtag_adda_trig.pnum_width = 10;
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u_virtual_jtag_adda_trig.pnum_width = 10;
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`endif
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`ifdef XILINX
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`ifdef AXI_IP
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// external ICON
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inout [35:0] icontrol0, icontrol1, icontrol2;
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`else
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// internal ICON
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wire [35:0] icontrol0, icontrol1, icontrol2;
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`endif
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// index 0, instantiate capture fifo, as output
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chipscope_vio_adda_fifo u_chipscope_vio_adda_fifo (
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.wr_in(capture_wr || pretrig_wr),
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.data_in(capture_in),
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.rd_in(pretrig_rd),
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.clk(clk),
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.icon_ctrl(icontrol0)
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);
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defparam
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u_chipscope_vio_adda_fifo.data_width = 82,
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u_chipscope_vio_adda_fifo.addr_width = 10,
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u_chipscope_vio_adda_fifo.al_full_val = 511;
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// index 1, instantiate capture mask, as input
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chipscope_vio_addr_mask u_chipscope_vio_addr_mask (
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// inclusive
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.mask_out0(addr_mask0),
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.mask_out1(addr_mask1),
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.mask_out2(addr_mask2),
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.mask_out3(addr_mask3),
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.mask_out4(addr_mask4),
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.mask_out5(addr_mask5),
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.mask_out6(addr_mask6),
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.mask_out7(addr_mask7),
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// exclusive
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.mask_out8(addr_mask8),
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.mask_out9(addr_mask9),
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.mask_out10(addr_mask10),
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.mask_out11(addr_mask11),
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.mask_out12(addr_mask12),
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.mask_out13(addr_mask13),
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.mask_out14(addr_mask14),
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.mask_out15(addr_mask15),
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.clk(clk),
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.icon_ctrl(icontrol1)
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);
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defparam
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u_chipscope_vio_addr_mask.mask_index = 4,
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u_chipscope_vio_addr_mask.mask_enabl = 4,
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u_chipscope_vio_addr_mask.addr_width = 32;
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// index 2, instantiate capture trigger, as input
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chipscope_vio_adda_trig u_chipscope_vio_adda_trig (
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.trig_out(trig_cond),
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.pnum_out(pretrig_num),
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.clk(clk),
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.icon_ctrl(icontrol2)
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);
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defparam
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u_chipscope_vio_adda_trig.trig_width = 56,
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u_chipscope_vio_adda_trig.pnum_width = 10;
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`ifdef AXI_IP
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// external ICON
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`else
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// internal ICON
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chipscope_icon u_chipscope_icon (
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.CONTROL0(icontrol0),
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.CONTROL1(icontrol1),
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.CONTROL2(icontrol2)
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);
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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