Line 27... |
Line 27... |
data_in
|
data_in
|
);
|
);
|
|
|
input clk;
|
input clk;
|
input wr_en,rd_en;
|
input wr_en,rd_en;
|
input [15:2] addr_in;
|
input [31:0] addr_in;
|
input [31:0] data_in;
|
input [31:0] data_in;
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
// Registers and wires announcment
|
// Registers and wires announcment
|
/////////////////////////////////////////////////
|
/////////////////////////////////////////////////
|
|
|
// for CPU bus signal buffer
|
// for CPU bus signal buffer
|
reg wr_en_d1,rd_en_d1;
|
reg wr_en_d1,rd_en_d1;
|
reg [15:2] addr_in_d1;
|
reg [31:0] addr_in_d1;
|
reg [31:0] data_in_d1;
|
reg [31:0] data_in_d1;
|
// for capture address mask
|
// for capture address mask
|
wire [35:0] addr_mask0,addr_mask1,addr_mask2 ,addr_mask3 ,addr_mask4 ,addr_mask5 ,addr_mask6 ,addr_mask7 , // inclusive
|
wire [35:0] addr_mask0,addr_mask1,addr_mask2 ,addr_mask3 ,addr_mask4 ,addr_mask5 ,addr_mask6 ,addr_mask7 , // inclusive
|
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15; // exclusive
|
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15; // exclusive
|
wire [15:0] addr_mask_en = {addr_mask15[32],addr_mask14[32],addr_mask13[32],addr_mask12[32],
|
wire [15:0] addr_mask_en = {addr_mask15[32],addr_mask14[32],addr_mask13[32],addr_mask12[32],
|
Line 48... |
Line 48... |
addr_mask3 [32],addr_mask2 [32],addr_mask1 [32],addr_mask0 [32]};
|
addr_mask3 [32],addr_mask2 [32],addr_mask1 [32],addr_mask0 [32]};
|
wire addr_wren = addr_mask15[35];
|
wire addr_wren = addr_mask15[35];
|
wire addr_rden = addr_mask15[34];
|
wire addr_rden = addr_mask15[34];
|
reg addr_mask_ok;
|
reg addr_mask_ok;
|
// for capture address+data trigger
|
// for capture address+data trigger
|
wire [55:0] trig_cond;
|
wire [71:0] trig_cond;
|
wire trig_aden = trig_cond[55];
|
wire trig_aden = trig_cond[71];
|
wire trig_daen = trig_cond[54];
|
wire trig_daen = trig_cond[70];
|
wire trig_wren = trig_cond[51];
|
wire trig_wren = trig_cond[67];
|
wire trig_rden = trig_cond[50];
|
wire trig_rden = trig_cond[66];
|
wire trig_en = trig_cond[49];
|
wire trig_en = trig_cond[65];
|
wire trig_set = trig_cond[48];
|
wire trig_set = trig_cond[64];
|
wire [15:0] trig_addr = trig_cond[47:32];
|
wire [31:0] trig_addr = trig_cond[63:32];
|
wire [31:0] trig_data = trig_cond[31:0];
|
wire [31:0] trig_data = trig_cond[31:0];
|
reg trig_cond_ok,trig_cond_ok_d1;
|
reg trig_cond_ok,trig_cond_ok_d1;
|
// for capture storage
|
// for capture storage
|
wire [81:0] capture_in;
|
wire [97:0] capture_in;
|
wire capture_wr;
|
wire capture_wr;
|
// for pretrigger capture
|
// for pretrigger capture
|
wire [9:0] pretrig_num;
|
wire [9:0] pretrig_num;
|
reg [9:0] pretrig_cnt;
|
reg [9:0] pretrig_cnt;
|
wire pretrig_full;
|
wire pretrig_full;
|
Line 86... |
Line 86... |
end
|
end
|
|
|
// address range based capture enable
|
// address range based capture enable
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2] && addr_mask_en[ 0]) ||
|
if (((addr_in[31:0]<=addr_mask0[31:0] && addr_in[31:0]>=addr_mask1[31:0] && addr_mask_en[ 0]) ||
|
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2] && addr_mask_en[ 1]) ||
|
(addr_in[31:0]<=addr_mask2[31:0] && addr_in[31:0]>=addr_mask3[31:0] && addr_mask_en[ 2]) ||
|
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2] && addr_mask_en[ 2]) ||
|
(addr_in[31:0]<=addr_mask4[31:0] && addr_in[31:0]>=addr_mask5[31:0] && addr_mask_en[ 4]) ||
|
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2] && addr_mask_en[ 3]) ||
|
(addr_in[31:0]<=addr_mask6[31:0] && addr_in[31:0]>=addr_mask7[31:0] && addr_mask_en[ 6])
|
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2] && addr_mask_en[ 4]) ||
|
|
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2] && addr_mask_en[ 5]) ||
|
|
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2] && addr_mask_en[ 6]) ||
|
|
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2] && addr_mask_en[ 7])
|
|
) //inclusive address range set with individual enable: addr_mask 0 - 7
|
) //inclusive address range set with individual enable: addr_mask 0 - 7
|
&&
|
&&
|
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2] || !addr_mask_en[ 8]) &&
|
((addr_in[31:0]>addr_mask8 [31:0] || addr_in[31:0]<addr_mask9 [31:0] || !addr_mask_en[ 8]) &&
|
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2] || !addr_mask_en[ 9]) &&
|
(addr_in[31:0]>addr_mask10[31:0] || addr_in[31:0]<addr_mask11[31:0] || !addr_mask_en[10]) &&
|
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2] || !addr_mask_en[10]) &&
|
(addr_in[31:0]>addr_mask12[31:0] || addr_in[31:0]<addr_mask13[31:0] || !addr_mask_en[12]) &&
|
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2] || !addr_mask_en[11]) &&
|
(addr_in[31:0]>addr_mask14[31:0] || addr_in[31:0]<addr_mask15[31:0] || !addr_mask_en[14])
|
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2] || !addr_mask_en[12]) &&
|
|
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2] || !addr_mask_en[13]) &&
|
|
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2] || !addr_mask_en[14]) &&
|
|
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2] || !addr_mask_en[15])
|
|
) //exclusive address range set with individual enable: addr_mask 8 - 15
|
) //exclusive address range set with individual enable: addr_mask 8 - 15
|
)
|
)
|
addr_mask_ok <= (addr_rden && rd_en) || (addr_wren && wr_en);
|
addr_mask_ok <= (addr_rden && rd_en) || (addr_wren && wr_en);
|
else
|
else
|
addr_mask_ok <= 0;
|
addr_mask_ok <= 0;
|
Line 123... |
Line 115... |
else if (trig_set==0) begin // trigger enabled and trigger stopped, trigger gate forced close
|
else if (trig_set==0) begin // trigger enabled and trigger stopped, trigger gate forced close
|
trig_cond_ok <= 0;
|
trig_cond_ok <= 0;
|
trig_cond_ok_d1 <= 0;
|
trig_cond_ok_d1 <= 0;
|
end
|
end
|
else begin // trigger enabled and trigger started, trigger gate conditional open
|
else begin // trigger enabled and trigger started, trigger gate conditional open
|
if ((trig_aden? trig_addr[15:2]==addr_in[15:2]: 1) && (trig_daen? trig_data==data_in: 1) &&
|
if ((trig_aden? trig_addr[31:0]==addr_in[31:0]: 1) && (trig_daen? trig_data==data_in: 1) &&
|
(trig_wren? wr_en : 1) && (trig_rden? rd_en : 1) &&
|
(trig_wren? wr_en : 1) && (trig_rden? rd_en : 1) &&
|
(rd_en || wr_en))
|
(rd_en || wr_en))
|
trig_cond_ok <= 1;
|
trig_cond_ok <= 1;
|
trig_cond_ok_d1 <= trig_cond_ok;
|
trig_cond_ok_d1 <= trig_cond_ok;
|
end
|
end
|
// trigger gate kept open until trigger stoped
|
// trigger gate kept open until trigger stoped
|
end
|
end
|
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
|
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
|
|
|
// generate capture wr_in
|
// generate capture wr_in
|
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
|
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[31:0],data_in_d1[31:0]};
|
assign capture_wr = trig_cond_ok_pulse || (addr_mask_ok && trig_cond_ok);
|
assign capture_wr = trig_cond_ok_pulse || (addr_mask_ok && trig_cond_ok);
|
|
|
// generate pre-trigger wr_in
|
// generate pre-trigger wr_in
|
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
|
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
|
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
|
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
|
Line 182... |
Line 174... |
.wr_in(capture_wr || pretrig_wr),
|
.wr_in(capture_wr || pretrig_wr),
|
.data_in(capture_in),
|
.data_in(capture_in),
|
.rd_in(pretrig_rd)
|
.rd_in(pretrig_rd)
|
);
|
);
|
defparam
|
defparam
|
u_virtual_jtag_adda_fifo.data_width = 82,
|
u_virtual_jtag_adda_fifo.data_width = 98,
|
u_virtual_jtag_adda_fifo.fifo_depth = 512,
|
u_virtual_jtag_adda_fifo.fifo_depth = 512,
|
u_virtual_jtag_adda_fifo.addr_width = 9,
|
u_virtual_jtag_adda_fifo.addr_width = 9,
|
u_virtual_jtag_adda_fifo.al_full_val = 511,
|
u_virtual_jtag_adda_fifo.al_full_val = 511,
|
u_virtual_jtag_adda_fifo.al_empt_val = 0;
|
u_virtual_jtag_adda_fifo.al_empt_val = 0;
|
|
|
Line 220... |
Line 212... |
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
.trig_out(trig_cond),
|
.trig_out(trig_cond),
|
.pnum_out(pretrig_num)
|
.pnum_out(pretrig_num)
|
);
|
);
|
defparam
|
defparam
|
u_virtual_jtag_adda_trig.trig_width = 56,
|
u_virtual_jtag_adda_trig.trig_width = 72,
|
u_virtual_jtag_adda_trig.pnum_width = 10;
|
u_virtual_jtag_adda_trig.pnum_width = 10;
|
`endif
|
`endif
|
|
|
`ifdef XILINX
|
`ifdef XILINX
|
|
|
Line 243... |
Line 235... |
.rd_in(pretrig_rd),
|
.rd_in(pretrig_rd),
|
.clk(clk),
|
.clk(clk),
|
.icon_ctrl(icontrol0)
|
.icon_ctrl(icontrol0)
|
);
|
);
|
defparam
|
defparam
|
u_chipscope_vio_adda_fifo.data_width = 82,
|
u_chipscope_vio_adda_fifo.data_width = 98,
|
u_chipscope_vio_adda_fifo.addr_width = 10,
|
u_chipscope_vio_adda_fifo.addr_width = 10,
|
u_chipscope_vio_adda_fifo.al_full_val = 511;
|
u_chipscope_vio_adda_fifo.al_full_val = 511;
|
|
|
// index 1, instantiate capture mask, as input
|
// index 1, instantiate capture mask, as input
|
chipscope_vio_addr_mask u_chipscope_vio_addr_mask (
|
chipscope_vio_addr_mask u_chipscope_vio_addr_mask (
|
Line 283... |
Line 275... |
.pnum_out(pretrig_num),
|
.pnum_out(pretrig_num),
|
.clk(clk),
|
.clk(clk),
|
.icon_ctrl(icontrol2)
|
.icon_ctrl(icontrol2)
|
);
|
);
|
defparam
|
defparam
|
u_chipscope_vio_adda_trig.trig_width = 56,
|
u_chipscope_vio_adda_trig.trig_width = 72,
|
u_chipscope_vio_adda_trig.pnum_width = 10;
|
u_chipscope_vio_adda_trig.pnum_width = 10;
|
|
|
`ifdef AXI_IP
|
`ifdef AXI_IP
|
// external ICON
|
// external ICON
|
`else
|
`else
|