| Line 19... |
Line 19... |
module up_monitor_wrapper (up_clk,up_wbe,up_csn,up_addr,up_data_io);
|
module up_monitor_wrapper (up_clk,up_wbe,up_csn,up_addr,up_data_io);
|
|
|
// common CPU bus interface
|
// common CPU bus interface
|
input up_clk;
|
input up_clk;
|
input up_wbe,up_csn; // negative logic
|
input up_wbe,up_csn; // negative logic
|
input [15:2] up_addr;
|
input [31:0] up_addr;
|
input [31:0] up_data_io;
|
input [31:0] up_data_io;
|
|
|
// filter out glitches on the line with extra 4 clocks
|
// filter out glitches on the line with extra 4 clocks
|
reg up_wbe_d1, up_wbe_d2, up_wbe_d3, up_wbe_d4;
|
reg up_wbe_d1, up_wbe_d2, up_wbe_d3, up_wbe_d4;
|
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
|
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
|
| Line 49... |
Line 49... |
rd_en_filtered <= (up_wbe_d2 & up_wbe_d3 & up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
|
rd_en_filtered <= (up_wbe_d2 & up_wbe_d3 & up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
|
rd_en_filtered_d1 <= rd_en_filtered;
|
rd_en_filtered_d1 <= rd_en_filtered;
|
end
|
end
|
|
|
// latch the data at rising edge of up_csn(negative logic)
|
// latch the data at rising edge of up_csn(negative logic)
|
reg [15:2] up_addr_latch;
|
reg [31:0] up_addr_latch;
|
reg [31:0] up_data_latch;
|
reg [31:0] up_data_latch;
|
always @(posedge up_csn) begin
|
always @(posedge up_csn) begin
|
up_addr_latch <= up_addr;
|
up_addr_latch <= up_addr;
|
up_data_latch <= up_data_io;
|
up_data_latch <= up_data_io;
|
end
|
end
|
|
|
// map to pipelined access interface
|
// map to pipelined access interface
|
wire clk = up_clk;
|
wire clk = up_clk;
|
wire wr_en = !wr_en_filtered & wr_en_filtered_d1; // falling edge of write_enable(positive logic)
|
wire wr_en = !wr_en_filtered & wr_en_filtered_d1; // falling edge of write_enable(positive logic)
|
wire rd_en = !rd_en_filtered & rd_en_filtered_d1; // falling edge of read_enable(positive logic)
|
wire rd_en = !rd_en_filtered & rd_en_filtered_d1; // falling edge of read_enable(positive logic)
|
wire [15:2] addr_in = up_addr_latch;
|
wire [31:0] addr_in = up_addr_latch;
|
wire [31:0] data_in = up_data_latch;
|
wire [31:0] data_in = up_data_latch;
|
|
|
up_monitor inst (
|
up_monitor inst (
|
.clk(clk),
|
.clk(clk),
|
.wr_en(wr_en),
|
.wr_en(wr_en),
|
