URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [chipscope_vio_adda_fifo.v] - Diff between revs 18 and 20
Show entire file |
Details |
Blame |
View Log
| Rev 18 |
Rev 20 |
| Line 15... |
Line 15... |
|
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
|
|
module chipscope_vio_adda_fifo(clk,wr_in,data_in,rd_in,icon_ctrl);
|
module chipscope_vio_adda_fifo(clk,wr_in,data_in,rd_in,icon_ctrl);
|
|
|
parameter data_width = 82,
|
parameter data_width = 98,
|
addr_width = 10,
|
addr_width = 10,
|
al_full_val = 511;
|
al_full_val = 511;
|
|
|
input clk;
|
input clk;
|
input wr_in, rd_in;
|
input wr_in, rd_in;
|
| Line 66... |
Line 66... |
|
|
chipscope_vio_fifo VIO_inst (
|
chipscope_vio_fifo VIO_inst (
|
.CONTROL(icon_ctrl), // INOUT BUS [35:0]
|
.CONTROL(icon_ctrl), // INOUT BUS [35:0]
|
.CLK(clk), // IN
|
.CLK(clk), // IN
|
.SYNC_OUT(ctrl_vi), // OUT BUS [1:0]
|
.SYNC_OUT(ctrl_vi), // OUT BUS [1:0]
|
.SYNC_IN(usedw_data_vo) // IN BUS [91:0]
|
.SYNC_IN(usedw_data_vo) // IN BUS [107:0]
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.