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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [chipscope_vio_adda_trig.v] - Diff between revs 18 and 20
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| Rev 18 |
Rev 20 |
| Line 15... |
Line 15... |
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module chipscope_vio_adda_trig(trig_out, pnum_out, clk, icon_ctrl);
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module chipscope_vio_adda_trig(trig_out, pnum_out, clk, icon_ctrl);
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parameter trig_width = 56;
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parameter trig_width = 72;
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parameter pnum_width = 10;
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parameter pnum_width = 10;
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output [trig_width-1:0] trig_out;
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output [trig_width-1:0] trig_out;
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output [pnum_width-1:0] pnum_out;
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output [pnum_width-1:0] pnum_out;
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Line 37... |
end
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end
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chipscope_vio_trig VIO_inst (
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chipscope_vio_trig VIO_inst (
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.CONTROL(icon_ctrl), // INOUT BUS [35:0]
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.CONTROL(icon_ctrl), // INOUT BUS [35:0]
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.CLK(clk), // IN
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.CLK(clk), // IN
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.SYNC_OUT(pnum_trig_vi) // OUT BUS [65:0]
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.SYNC_OUT(pnum_trig_vi) // OUT BUS [81:0]
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);
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);
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endmodule
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endmodule
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