URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2012 Xilinx, Inc.
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// Copyright (c) 2014 Xilinx, Inc.
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// All Rights Reserved
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// All Rights Reserved
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// ____ ____
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// / /\/ /
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 14.2
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// \ \ \/ Version : 14.3
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// \ \ Application: Xilinx CORE Generator
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// \ \ Application: Xilinx CORE Generator
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// / / Filename : chipscope_vio_trig.v
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// / / Filename : chipscope_vio_trig.v
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// /___/ /\ Timestamp : Tue Nov 20 10:37:58 中国标准时间 2012
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// /___/ /\ Timestamp : Fri Feb 07 14:57:09 中国标准时间 2014
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// \ \ / \
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// \ \ / \
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// \___\/\___\
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// \___\/\___\
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//
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//
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// Design Name: Verilog Synthesis Wrapper
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// Design Name: Verilog Synthesis Wrapper
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module chipscope_vio_trig(
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module chipscope_vio_trig(
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CONTROL,
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CONTROL,
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CLK,
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CLK,
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SYNC_OUT);
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SYNC_OUT) /* synthesis syn_black_box syn_noprune=1 */;
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inout [35 : 0] CONTROL;
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inout [35 : 0] CONTROL;
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input CLK;
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input CLK;
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output [65 : 0] SYNC_OUT;
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output [81 : 0] SYNC_OUT;
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endmodule
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endmodule
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