URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [chipscope_vio_trig.xco] - Diff between revs 18 and 20

Rev 18	Rev 20
Line 1...	Line 1...
`##############################################################`	`##############################################################`
`#`	`#`
`# Xilinx Core Generator version 14.2`	`# Xilinx Core Generator version 14.3`
`# Date: Tue Nov 20 02:37:14 2012`	`# Date: Fri Feb 07 06:56:23 2014`
`#`	`#`
`##############################################################`	`##############################################################`
`#`	`#`
`# This file contains the customisation parameters for a`	`# This file contains the customisation parameters for a`
`# Xilinx CORE Generator IP GUI. It is strongly recommended`	`# Xilinx CORE Generator IP GUI. It is strongly recommended`
Line 48...	Line 48...
`CSET enable_synchronous_input_port=false`	`CSET enable_synchronous_input_port=false`
`CSET enable_synchronous_output_port=true`	`CSET enable_synchronous_output_port=true`
`CSET example_design=true`	`CSET example_design=true`
`CSET invert_clock_input=false`	`CSET invert_clock_input=false`
`CSET synchronous_input_port_width=8`	`CSET synchronous_input_port_width=8`
`CSET synchronous_output_port_width=66`	`CSET synchronous_output_port_width=82`
`# END Parameters`	`# END Parameters`
`# BEGIN Extra information`	`# BEGIN Extra information`
`MISC pkg_timestamp=2012-07-21T03:12:17Z`	`MISC pkg_timestamp=2012-10-12T23:08:55Z`
`# END Extra information`	`# END Extra information`
`GENERATE`	`GENERATE`
`# CRC: fa7ecb23`	`# CRC: d79507a`
`# CRC: d79507a`	`# CRC: d79507a`