URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [pcores/] [bustap_jtag_v1_00_a/] [hdl/] [verilog/] [bustap_jtag.v] - Diff between revs 18 and 20

Rev 18	Rev 20
Line 144...	Line 144...

`// map to pipelined access interface`	`// map to pipelined access interface`
`wire clk = ACLK;`	`wire clk = ACLK;`
`wire wr_en = wr_pulse;`	`wire wr_en = wr_pulse;`
`wire rd_en = rd_pulse;`	`wire rd_en = rd_pulse;`
`wire [15:2] addr_in = addr_latch[15:2];`	`wire [31:0] addr_in = addr_latch[31:0];`
`wire [31:0] data_in = data_latch;`	`wire [31:0] data_in = data_latch;`

`up_monitor inst (`	`up_monitor inst (`
`.clk(clk),`	`.clk(clk),`
`.wr_en(wr_en),`	`.wr_en(wr_en),`