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https://opencores.org/ocsvn/bw_tiff_compression/bw_tiff_compression/trunk
[/] [bw_tiff_compression/] [trunk/] [var_width_RAM.vhd] - Diff between revs 11 and 12
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| Rev 11 |
Rev 12 |
| Line 140... |
Line 140... |
-- "0111" => 3
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-- "0111" => 3
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-- "1111" => 4 = 0
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-- "1111" => 4 = 0
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if reset_i = '1' then
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if reset_i = '1' then
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mux_sel <= (others => '0');
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mux_sel <= (others => '0');
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-- if wr4_i = '0' and wr3_i = '0' and wr2_i = '0' and wr1_i = '0' then
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-- mux_sel <= mux_sel - to_unsigned(0,2);
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elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '0' and wr1_i = '1' then
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elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '0' and wr1_i = '1' then
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mux_sel <= mux_sel - to_unsigned(1,2);
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mux_sel <= mux_sel - to_unsigned(1,2);
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elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '1' and wr1_i = '1' then
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elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '1' and wr1_i = '1' then
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mux_sel <= mux_sel - to_unsigned(2,2);
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mux_sel <= mux_sel - to_unsigned(2,2);
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elsif wr4_i = '0' and wr3_i = '1' and wr2_i = '1' and wr1_i = '1' then
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elsif wr4_i = '0' and wr3_i = '1' and wr2_i = '1' and wr1_i = '1' then
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mux_sel <= mux_sel - to_unsigned(3,2);
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mux_sel <= mux_sel - to_unsigned(3,2);
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-- elsif wr4_i = '1' and wr3_i = '1' and wr2_i = '1' and wr1_i = '1' then
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-- mux_sel <= mux_sel - to_unsigned(4,2);
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else
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else
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mux_sel <= mux_sel - to_unsigned(0,2);
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mux_sel <= mux_sel - to_unsigned(0,2);
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end if;
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end if;
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end if;
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end if;
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end process mux_sel_cnt_process;
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end process mux_sel_cnt_process;
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