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[/] [connect-6/] [trunk/] [BUILD_SCC/] [DE2/] [async_receiver_altera.v] - Diff between revs 4 and 7
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module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
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module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
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input clk, RxD;
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input clk, RxD;
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output RxD_data_ready; // onc clock pulse when RxD_data is valid
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output RxD_data_ready; // onc clock pulse when RxD_data is valid
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output [7:0] RxD_data;
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output [7:0] RxD_data;
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parameter ClkFrequency = 50000000; // 50MHz
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//parameter ClkFrequency = 50000000; // 50MHz
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//parameter ClkFrequency = 27000000; // 27MHz
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parameter ClkFrequency = 27000000; // 27MHz
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parameter Baud = 115200;
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parameter Baud = 115200;
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// We also detect if a gap occurs in the received stream of characters
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// We also detect if a gap occurs in the received stream of characters
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// That can be useful if multiple characters are sent in burst
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// That can be useful if multiple characters are sent in burst
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// so that multiple characters can be treated as a "packet"
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// so that multiple characters can be treated as a "packet"
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