Subversion Repositories copyblaze

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-- Company: 

--

-- File: cp_FullAdder.vhd

--

-- Description:

--      projet copyblaze

--      1 bit Full adder

--

-- File history:

-- v1.0: 14/10/11: Creation

--

-- Targeted device: ProAsic A3P250 VQFP100

-- Author: AbdAllah Meziti

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library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use     work.Usefull_Pkg.all;           -- Usefull Package

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-- Entity: cp_FullAdder

--

-- Description:

--      

--      REMARQUE:

--

--      

-- History:

-- 14/10/11 AM: Creation

-- ---------------------

-- xx/xx/xx AM: 

--                              

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entity cp_FullAdder is

        port (

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        -- Signaux Fonctionels

        --------------------------------------------------------------------------------

                Ci_i            : in std_ulogic;

                A_i                     : in std_ulogic;

                B_i                     : in std_ulogic;

                Co_o            : out std_ulogic;

                S_o                     : out std_ulogic

        );

end cp_FullAdder;

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-- Architecture: RTL

-- of entity : cp_FullAdder

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architecture rtl of cp_FullAdder is

        --------------------------------------------------------------------------------

        -- Définition des fonctions

        --------------------------------------------------------------------------------

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        -- Définition des constantes

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        -- Définition des signaux interne

        --------------------------------------------------------------------------------

        --------------------------------------------------------------------------------

        -- Déclaration des composants

        --------------------------------------------------------------------------------

begin

        --------------------------------------------------------------------------------

        -- Full adder

        --------------------------------------------------------------------------------

        -- SUM

        S_o             <=      A_i xor B_i xor Ci_i;

        -- CARRY

        Co_o    <=      (A_i and B_i) or (B_i and Ci_i) or (A_i and Ci_i);

end rtl;