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[/] [crcahb/] [trunk/] [rtl/] [bit_reversal.v] - Diff between revs 2 and 3

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//////////////////////////////////////////////////////////////////
 
////
 
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////    CRCAHB CORE BLOCK
 
////
 
////
 
////
 
//// This file is part of the APB to I2C project
 
////
 
//// http://www.opencores.org/cores/apbi2c/
 
////
 
////
 
////
 
//// Description
 
////
 
//// Implementation of APB IP core according to
 
////
 
//// crcahb IP core specification document.
 
////
 
////
 
////
 
//// To Do: Things are right here but always all block can suffer changes
 
////
 
////
 
////
 
////
 
////
 
//// Author(s): -  Julio Cesar 
 
////
 
///////////////////////////////////////////////////////////////// 
 
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
 
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//// This source file may be used and distributed without
 
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//// the original copyright notice and the associated disclaimer.
 
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//// This source file is free software; you can redistribute it
 
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//// and/or modify it under the terms of the GNU Lesser General
 
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//// Public License as published by the Free Software Foundation;
 
//// either version 2.1 of the License, or (at your option) any
 
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//// later version.
 
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//// This source is distributed in the hope that it will be
 
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
 
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
 
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//// PURPOSE. See the GNU Lesser General Public License for more
 
//// details.
 
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//// You should have received a copy of the GNU Lesser General
 
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//// Public License along with this source; if not, download it
 
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//// from http://www.opencores.org/lgpl.shtml
 
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///////////////////////////////////////////////////////////////////
 
 
`define size ((DATA_SIZE/4) * (2 ** (type - 1)))
`define size ((DATA_SIZE/4) * (2 ** (type - 1)))
 
 
module bit_reversal
module bit_reversal
#(
#(
        parameter DATA_SIZE = 32
        parameter DATA_SIZE = 32

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