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cas core
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csa core
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===============
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===============
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attached is a cas core implementation in verilog. it implement
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attached is a cas core implementation in verilog. it implement
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a cas descrambler
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a cas descrambler
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reference:
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reference:
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csa.c and csa.h in vlc opensource project.
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csa.c and csa.h in vlc opensource project.
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archecture
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===============
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the top module is the group_decrypt.
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Status
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Status
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======
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======
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7-sep-2007 added key csa_ComputeKey
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7-sep-2007 added key csa_ComputeKey
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4-May-2009 group_decrypt module pass modelsim basicly
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How to test this core
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========================
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this project mainly has three dictories:
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rtl bench and sw_sim
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every module have a file in these dictories
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i simualted my modules by open source program veriwell and iverilog in the early time , but
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they don't work well, and generate some error result sometime. so i use the modelsim now.
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1) generate test data
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cd
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make MODULE= preare_ ( for example: make MODULE=group_decrypt preare_group_decrypt )
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this command will generate a binary file /test_dat/.in
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(for example: test_dat/group_decrypt.in )
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2) software simulate
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cd /sw_sim
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make MODULE= tt
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this command will compile and run the module test program
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and will generate a binary output file /test_dat/.out.sw
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(for example: test_dat/group_decrypt.out.sw )
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3) run test bench
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start the modelsim (i use the modelsim 6.2b LE)
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cd /modelsim6.2b
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run .do tcl script, ( for example: do group_decrypt.do )
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and will generate a binary output file /test_dat/.out.v
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if the two output file is same, this module is pass
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Directory Structure
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Directory Structure
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===================
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===================
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[core_root]
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[core_root]
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+-doc Documentation
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+-doc Documentation
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+-bench--+ Test Bench
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+-bench--+ Test Bench
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+-rtl----+ Core RTL Sources
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+-rtl----+ Core RTL Sources
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+-modelsim6.2b--+ modelsim files
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+-quartus10--+ altera quartus 10.1 project file
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+-sw_sim-----+ the pc programs for generate some test data
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+-test_data--+ the test datas for test bench
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about the author
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about the author
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================
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================
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if you have some issues and advance, please contact me:
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if you have some issues and advance, please contact me:
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