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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Diff between revs 33 and 38
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| Rev 33 |
Rev 38 |
| Line 52... |
Line 52... |
// usb interface
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// usb interface
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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assign slcs =1'h0;
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assign slcs =1'h0;
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assign pktend=1'h1;
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assign pktend=1'h1;
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`define EP2_W 2'h0
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`define EP2_W 2'h3
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`define EP6_R 2'h1
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`define EP6_R 2'h2
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`define EP8_R 2'h2
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`define EP8_R 2'h1
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`define NO_ACT 2'h3
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`define NO_ACT 2'h0
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reg [ 1:0] last_action;
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reg [ 1:0] last_action;
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reg [15:0] usb_dat_out;
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reg [15:0] usb_dat_out;
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reg [15:0] usb_dat_in;
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reg [15:0] usb_dat_in;
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| Line 88... |
Line 88... |
sloe<=1'h1;
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sloe<=1'h1;
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fifoadr<=2'h0;
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fifoadr<=2'h0;
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slwr<=1'h0;
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slwr<=1'h0;
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slrd<=1'h1;
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slrd<=1'h1;
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last_action<=`EP2_W;
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last_action<=`EP2_W;
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end
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end
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else
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else
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begin
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begin
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sloe<=1'h1;
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sloe<=1'h1;
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fifoadr<=2'h0;
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fifoadr<=2'h0;
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slwr<=1'h1;
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slwr<=1'h1;
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slrd<=1'h1;
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slrd<=1'h1;
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last_action<=`NO_ACT;
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last_action<=`NO_ACT;
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end
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end
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always @(posedge usbclk)
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always @(posedge usbclk)
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if(last_action==`EP8_R )
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if(last_action==`EP8_R )
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usb_dat_in<=fd;
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usb_dat_in<=fd;
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assign fd=(sloe)?usb_dat_out:16'hzzzz;
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assign fd=(sloe)?usb_dat_out:16'hzzzz;
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