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`include "../bench/timescale.v"
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// this key_schedule module
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// this key_schedule module
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module key_schedule(clk,rst,start,i_ck,busy,done,o_kk);
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module key_schedule(clk,rst,start,i_ck,busy,done,o_kk);
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input clk;
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input clk;
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input rst;
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input rst;
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input start;
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input start;
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cnt <= 3'h5;
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cnt <= 3'h5;
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o_kk <= {o_kk [(6*8)*8-1:8*0], i_ck};
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o_kk <= {o_kk [(6*8)*8-1:8*0], i_ck};
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busy <= 1'h1;
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busy <= 1'h1;
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ok_d <= oki;
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ok_d <= oki;
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o_kk <= {o_kk [(6*8)*8-1:8*0],
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o_kk <= {o_kk [(6*8)*8-1:8*0],
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oki ^ 64'h0606060606060606};
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i_ck ^ 64'h0606060606060606};
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end
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end
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if(busy)
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if(busy)
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begin
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begin
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o_kk <= {o_kk [(6*8)*8-1:8*0],
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o_kk <= {o_kk [(6*8)*8-1:8*0],
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cnt <= cnt - 3'h1;
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cnt <= cnt - 3'h1;
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ok_d <= okd;
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ok_d <= okd;
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end
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end
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end
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end
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end
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end
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// wire [64*8-1:0] kb;
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// assign kb[(8*8)*8-1:(7*8)*8] = i_ck;
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//
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// key_perm k1( .i_key(kb[(8*8)*8-1:(7*8)*8]) ,.o_key(kb[(7*8)*8-1:(6*8)*8]));
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// key_perm k2( .i_key(kb[(7*8)*8-1:(6*8)*8]) ,.o_key(kb[(6*8)*8-1:(5*8)*8]));
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// key_perm k3( .i_key(kb[(6*8)*8-1:(5*8)*8]) ,.o_key(kb[(5*8)*8-1:(4*8)*8]));
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// key_perm k4( .i_key(kb[(5*8)*8-1:(4*8)*8]) ,.o_key(kb[(4*8)*8-1:(3*8)*8]));
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// key_perm k5( .i_key(kb[(4*8)*8-1:(3*8)*8]) ,.o_key(kb[(3*8)*8-1:(2*8)*8]));
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// key_perm k6( .i_key(kb[(3*8)*8-1:(2*8)*8]) ,.o_key(kb[(2*8)*8-1:(1*8)*8]));
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// key_perm k7( .i_key(kb[(2*8)*8-1:(1*8)*8]) ,.o_key(kb[(1*8)*8-1:(0*8)*8]));
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//
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// assign o_kk [(1*8)*8-1:(0*8)*8] = kb[(2*8)*8-1:(1*8)*8] ^ 64'h0000000000000000;
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// assign o_kk [(2*8)*8-1:(1*8)*8] = kb[(3*8)*8-1:(2*8)*8] ^ 64'h0101010101010101;
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// assign o_kk [(3*8)*8-1:(2*8)*8] = kb[(4*8)*8-1:(3*8)*8] ^ 64'h0202020202020202;
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// assign o_kk [(4*8)*8-1:(3*8)*8] = kb[(5*8)*8-1:(4*8)*8] ^ 64'h0303030303030303;
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// assign o_kk [(5*8)*8-1:(4*8)*8] = kb[(6*8)*8-1:(5*8)*8] ^ 64'h0404040404040404;
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// assign o_kk [(6*8)*8-1:(5*8)*8] = kb[(7*8)*8-1:(6*8)*8] ^ 64'h0505050505050505;
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// assign o_kk [(7*8)*8-1:(6*8)*8] = kb[(8*8)*8-1:(7*8)*8] ^ 64'h0606060606060606;
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endmodule
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endmodule
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