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`include "../bench/timescale.v"
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`include "../bench/timescale.v"
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// this key_schedule module
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// this key_schedule module
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module key_schedule(clk,rst,start,i_ck,busy,done,o_kk);
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module key_schedule(clk,rst,start,ck,busy,done,kk);
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input clk;
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input clk; // main clock
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input rst;
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input rst; // reset , high active
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input start;
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input start; // start key
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input [ 8*8-1:0] i_ck;
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input [ 8*8-1:0] ck;
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output busy;
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output busy;
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output done;
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output done; // one clck width
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output [56*8-1:0] o_kk;
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output [56*8-1:0] kk;
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reg [56*8-1:0] o_kk;
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wire [56*8-1:0] kk;
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reg [ 2:0] cnt;
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wire [ 8*8-1:0] ik;
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wire [ 8*8-1:0] okd;
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wire [ 8*8-1:0] oki;
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reg [ 8*8-1:0] ok_d;
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reg done;
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reg busy;
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reg busy;
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key_perm kpo(.i_key(ok_d), .o_key(okd));
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////////////////////////////////////////////////////////////////////////////////
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key_perm kpi(.i_key(i_ck), .o_key(oki));
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// internal variable
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////////////////////////////////////////////////////////////////////////////////
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reg [56*8-1:0] kk_arry; // the key array
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reg [ 2:0] cnt;
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wire [ 8*8-1:0] next_kk; // the next roundl kk
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always @(posedge clk)
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always @(posedge clk)
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begin
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done <= 1'h0;
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if(rst)
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if(rst)
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begin
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o_kk <= 448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
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cnt <= 3'h0;
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cnt <= 3'h0;
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ok_d <= 64'h0000000000000000;
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else if(start)
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busy <= 1'h0;
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cnt <= 3'h6;
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end
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else if(cnt!=3'h0)
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else
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cnt <= cnt-3'h1;
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begin
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if(cnt==3'h0 && busy)
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begin
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busy <= 1'h0;
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done <= 1'h1;
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end
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if(start & ~busy)
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always @(posedge clk)
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begin
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if(rst)
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cnt <= 3'h5;
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busy=1'h0;
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o_kk <= {o_kk [(6*8)*8-1:8*0], i_ck};
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else if(start)
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busy <= 1'h1;
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busy <= 1'h1;
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ok_d <= oki;
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else if(cnt==3'h0)
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o_kk <= {o_kk [(6*8)*8-1:8*0],
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busy<=1'h0;
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i_ck ^ 64'h0606060606060606};
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end
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assign done=busy & (cnt==3'h0);
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if(busy)
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always @(posedge clk )
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begin
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if(rst)
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o_kk <= {o_kk [(6*8)*8-1:8*0],
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kk_arry<=448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
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ok_d ^ {
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else if(start)
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5'h00, cnt,
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kk_arry<={kk_arry[48*8-1:0],ck};
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5'h00, cnt,
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else if(cnt!=3'h0)
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5'h00, cnt,
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kk_arry<={kk_arry[48*8-1:0],next_kk};
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5'h00, cnt,
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5'h00, cnt,
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assign kk=kk_arry ^ {
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5'h00, cnt,
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64'h0606060606060606,
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5'h00, cnt,
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64'h0505050505050505,
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5'h00, cnt
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64'h0404040404040404,
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}
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64'h0303030303030303,
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64'h0202020202020202,
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64'h0101010101010101,
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64'h0000000000000000
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};
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};
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if(cnt!=3'h0)
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//assign busy=cnt!=3'h0;
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cnt <= cnt - 3'h1;
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ok_d <= okd;
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key_perm kpi(.i_key(kk_arry[8*8-1:0]), .o_key(next_kk));
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end
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end
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end
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endmodule
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endmodule
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