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Line 52... |
#define LGWIDTH TST_QTRSTAGE_LGWIDTH
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#define LGWIDTH TST_QTRSTAGE_LGWIDTH
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#define ASIZ 32
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#define ASIZ 32
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#define AMSK (ASIZ-1)
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#define AMSK (ASIZ-1)
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#ifdef NEW_VERILATOR
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#define VVAR(A) qtrstage__DOT_ ## A
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#else
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#define VVAR(A) v__DOT_ ## A
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#endif
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#define sum_r VVAR(_sum_r)
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#define sum_i VVAR(_sum_i)
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#define diff_r VVAR(_diff_r)
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#define diff_i VVAR(_diff_i)
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#define pipeline VVAR(_pipeline)
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#define iaddr VVAR(_iaddr)
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#define imem VVAR(_imem)
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#define wait_for_sync VVAR(_wait_for_sync)
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class QTRTEST_TB {
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class QTRTEST_TB {
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public:
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public:
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Vqtrstage *m_qstage;
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Vqtrstage *m_qstage;
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unsigned long m_data[ASIZ];
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unsigned long m_data[ASIZ];
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int m_addr, m_offset;
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int m_addr, m_offset;
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Line 163... |
tick();
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tick();
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printf("k=%4d: ISYNC=%d, IN = %08x, OUT =%09lx, SYNC=%d\t%5x,%5x,%5x,%5x\t%x %4x %8x %d\n",
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printf("k=%4d: ISYNC=%d, IN = %08x, OUT =%09lx, SYNC=%d\t%5x,%5x,%5x,%5x\t%x %4x %8x %d\n",
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(m_addr-m_offset), isync, m_qstage->i_data,
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(m_addr-m_offset), isync, m_qstage->i_data,
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m_qstage->o_data, m_qstage->o_sync,
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m_qstage->o_data, m_qstage->o_sync,
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m_qstage->v__DOT__sum_r,
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m_qstage->v__DOT__sum_i,
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m_qstage->sum_r,
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m_qstage->v__DOT__diff_r,
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m_qstage->sum_i,
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m_qstage->v__DOT__diff_i,
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m_qstage->diff_r,
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m_qstage->v__DOT__pipeline,
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m_qstage->diff_i,
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m_qstage->v__DOT__iaddr,
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m_qstage->pipeline,
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m_qstage->v__DOT__imem,
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m_qstage->iaddr,
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m_qstage->v__DOT__wait_for_sync);
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m_qstage->imem,
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m_qstage->wait_for_sync);
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check_results();
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check_results();
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}
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}
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void test(int ir0, int ii0) {
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void test(int ir0, int ii0) {
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