| Line 245... |
Line 245... |
"//\n%s"
|
"//\n%s"
|
"//\n",
|
"//\n",
|
prjname, creator);
|
prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module truncate(i_clk, i_ce, i_val, o_val);\n"
|
"module truncate(i_clk, i_ce, i_val, o_val);\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
| Line 286... |
Line 287... |
"//\n%s"
|
"//\n%s"
|
"//\n",
|
"//\n",
|
prjname, creator);
|
prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module roundhalfup(i_clk, i_ce, i_val, o_val);\n"
|
"module roundhalfup(i_clk, i_ce, i_val, o_val);\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
| Line 318... |
Line 320... |
"\t\tassign\tfirst_lost_bit = i_val[(IWID-SHIFT-OWID-1)];\n"
|
"\t\tassign\tfirst_lost_bit = i_val[(IWID-SHIFT-OWID-1)];\n"
|
"\n"
|
"\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\telse\n"
|
"\t\t\t\telse\n"
|
"\t\t\t\t\to_val <= rounded_up; // even value\n"
|
"\t\t\t\t\to_val <= rounded_up; // even value\n"
|
"\t\t\tend\n"
|
"\t\t\tend\n"
|
"\n"
|
"\n"
|
| Line 364... |
Line 366... |
"//\n%s"
|
"//\n%s"
|
"//\n",
|
"//\n",
|
prjname, creator);
|
prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module roundfromzero(i_clk, i_ce, i_val, o_val);\n"
|
"module roundfromzero(i_clk, i_ce, i_val, o_val);\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
| Line 408... |
Line 411... |
"\t\tassign\tsign_bit = i_val[(IWID-1)];\n"
|
"\t\tassign\tsign_bit = i_val[(IWID-1)];\n"
|
"\n"
|
"\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\telse if (sign_bit)\n"
|
"\t\t\t\telse if (sign_bit)\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\telse\n"
|
"\t\t\t\telse\n"
|
"\t\t\t\t\to_val <= rounded_up;\n"
|
"\t\t\t\t\to_val <= rounded_up;\n"
|
| Line 431... |
Line 434... |
"\t\tassign\tother_lost_bits = i_val[(IWID-SHIFT-OWID-2):0];\n"
|
"\t\tassign\tother_lost_bits = i_val[(IWID-SHIFT-OWID-2):0];\n"
|
"\n"
|
"\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\telse if (|other_lost_bits) // Round up to\n"
|
"\t\t\t\telse if (|other_lost_bits) // Round up to\n"
|
"\t\t\t\t\to_val <= rounded_up; // closest value\n"
|
"\t\t\t\t\to_val <= rounded_up; // closest value\n"
|
"\t\t\t\telse if (sign_bit)\n"
|
"\t\t\t\telse if (sign_bit)\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
| Line 473... |
Line 476... |
"//\n%s"
|
"//\n%s"
|
"//\n",
|
"//\n",
|
prjname, creator);
|
prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module convround(i_clk, i_ce, i_val, o_val);\n"
|
"module convround(i_clk, i_ce, i_val, o_val);\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tparameter\tIWID=16, OWID=8, SHIFT=0;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
"\tinput\t\tsigned\t[(IWID-1):0]\ti_val;\n"
|
| Line 522... |
Line 526... |
"\t\tassign\tfirst_lost_bit = i_val[0];\n"
|
"\t\tassign\tfirst_lost_bit = i_val[0];\n"
|
"\n"
|
"\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\telse if (last_valid_bit)// Round up to nearest\n"
|
"\t\t\t\telse if (last_valid_bit)// Round up to nearest\n"
|
"\t\t\t\t\to_val <= rounded_up; // even value\n"
|
"\t\t\t\t\to_val <= rounded_up; // even value\n"
|
"\t\t\t\telse // else round down to the nearest\n"
|
"\t\t\t\telse // else round down to the nearest\n"
|
"\t\t\t\t\to_val <= truncated_value; // even value\n"
|
"\t\t\t\t\to_val <= truncated_value; // even value\n"
|
| Line 545... |
Line 549... |
"\t\tassign\tother_lost_bits = i_val[(IWID-SHIFT-OWID-2):0];\n"
|
"\t\tassign\tother_lost_bits = i_val[(IWID-SHIFT-OWID-2):0];\n"
|
"\n"
|
"\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\talways @(posedge i_clk)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tif (i_ce)\n"
|
"\t\t\tbegin\n"
|
"\t\t\tbegin\n"
|
"\t\t\t\tif (~first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\tif (!first_lost_bit) // Round down / truncate\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\t\to_val <= truncated_value;\n"
|
"\t\t\t\telse if (|other_lost_bits) // Round up to\n"
|
"\t\t\t\telse if (|other_lost_bits) // Round up to\n"
|
"\t\t\t\t\to_val <= rounded_up; // closest value\n"
|
"\t\t\t\t\to_val <= rounded_up; // closest value\n"
|
"\t\t\t\telse if (last_valid_bit) // Round up to\n"
|
"\t\t\t\telse if (last_valid_bit) // Round up to\n"
|
"\t\t\t\t\to_val <= rounded_up; // nearest even\n"
|
"\t\t\t\t\to_val <= rounded_up; // nearest even\n"
|
| Line 594... |
Line 598... |
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n",
|
"//\n",
|
(dbg)?"_dbg":"", prjname, creator);
|
(dbg)?"_dbg":"", prjname, creator);
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
|
|
fprintf(fp,
|
fprintf(fp,
|
"module\tqtrstage%s(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync%s);\n"
|
"module\tqtrstage%s(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync%s);\n"
|
"\tparameter IWIDTH=%d, OWIDTH=IWIDTH+1;\n"
|
"\tparameter IWIDTH=%d, OWIDTH=IWIDTH+1;\n"
|
"\t// Parameters specific to the core that should be changed when this\n"
|
"\t// Parameters specific to the core that should be changed when this\n"
|
| Line 674... |
Line 679... |
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
"\t\tif (i_rst)\n"
|
"\t\tif (i_rst)\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
"\t\t\twait_for_sync <= 1\'b1;\n"
|
"\t\t\twait_for_sync <= 1\'b1;\n"
|
"\t\t\tiaddr <= 0;\n"
|
"\t\t\tiaddr <= 0;\n"
|
"\t\tend else if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
|
"\t\tend else if ((i_ce)&&((!wait_for_sync)||(i_sync)))\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
"\t\t\tiaddr <= iaddr + { {(LGWIDTH-1){1\'b0}}, 1\'b1 };\n"
|
"\t\t\tiaddr <= iaddr + { {(LGWIDTH-1){1\'b0}}, 1\'b1 };\n"
|
"\t\t\twait_for_sync <= 1\'b0;\n"
|
"\t\t\twait_for_sync <= 1\'b0;\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
| Line 809... |
Line 814... |
"// o_sync Output synchronization signal.\n"
|
"// o_sync Output synchronization signal.\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", (dbg)?"_dbg":"", prjname, creator);
|
"//\n", (dbg)?"_dbg":"", prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module\tdblstage%s(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync%s);\n"
|
"module\tdblstage%s(i_clk, i_rst, i_ce, i_sync, i_left, i_right, o_left, o_right, o_sync%s);\n"
|
"\tparameter\tIWIDTH=%d,OWIDTH=IWIDTH+1, SHIFT=%d;\n"
|
"\tparameter\tIWIDTH=%d,OWIDTH=IWIDTH+1, SHIFT=%d;\n"
|
"\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
|
"\tinput\t\ti_clk, i_rst, i_ce, i_sync;\n"
|
"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
|
"\tinput\t\t[(2*IWIDTH-1):0]\ti_left, i_right;\n"
|
| Line 955... |
Line 961... |
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", prjname, creator);
|
"//\n", prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module shiftaddmpy(i_clk, i_ce, i_a, i_b, o_r);\n"
|
"module shiftaddmpy(i_clk, i_ce, i_a, i_b, o_r);\n"
|
"\tparameter\tAWIDTH=%d,BWIDTH=", TST_SHIFTADDMPY_AW);
|
"\tparameter\tAWIDTH=%d,BWIDTH=", TST_SHIFTADDMPY_AW);
|
#ifdef TST_SHIFTADDMPY_BW
|
#ifdef TST_SHIFTADDMPY_BW
|
fprintf(fp, "%d;\n", TST_SHIFTADDMPY_BW);
|
fprintf(fp, "%d;\n", TST_SHIFTADDMPY_BW);
|
| Line 1057... |
Line 1064... |
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", fname, prjname, creator);
|
"//\n", fname, prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module bimpy(i_clk, i_ce, i_a, i_b, o_r);\n"
|
"module bimpy(i_clk, i_ce, i_a, i_b, o_r);\n"
|
"\tparameter\tBW=18, // Number of bits in i_b\n"
|
"\tparameter\tBW=18, // Number of bits in i_b\n"
|
"\t\t\tLUTB=2; // Number of bits in i_a for our LUT multiply\n"
|
"\t\t\tLUTB=2; // Number of bits in i_a for our LUT multiply\n"
|
"\tinput\t\t\t\ti_clk, i_ce;\n"
|
"\tinput\t\t\t\ti_clk, i_ce;\n"
|
| Line 1112... |
Line 1120... |
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", fname, prjname, creator);
|
"//\n", fname, prjname, creator);
|
|
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module longbimpy(i_clk, i_ce, i_a, i_b, o_r);\n"
|
"module longbimpy(i_clk, i_ce, i_a, i_b, o_r);\n"
|
"\tparameter AW=%d, // The width of i_a, min width is 5\n"
|
"\tparameter AW=%d, // The width of i_a, min width is 5\n"
|
"\t\t\tBW=", TST_LONGBIMPY_AW);
|
"\t\t\tBW=", TST_LONGBIMPY_AW);
|
#ifdef TST_LONGBIMPY_BW
|
#ifdef TST_LONGBIMPY_BW
|
| Line 1226... |
Line 1235... |
"\tassign\tw_r = (r_s[TLEN-1]) ? (-acc[TLEN-2]) : acc[TLEN-2];\n"
|
"\tassign\tw_r = (r_s[TLEN-1]) ? (-acc[TLEN-2]) : acc[TLEN-2];\n"
|
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
"\t\tif (i_ce)\n"
|
"\t\tif (i_ce)\n"
|
"\t\t\to_r <= w_r[(AW+BW-1):0];\n"
|
"\t\t\to_r <= w_r[(AW+BW-1):0];\n"
|
"\n"
|
"\n"
|
|
"\tgenerate if (IW > AW)\n"
|
|
"\tbegin : VUNUSED\n"
|
|
"\t\t// verilator lint_off UNUSED\n"
|
|
"\t\twire\t[(IW-AW)-1:0]\tunused;\n"
|
|
"\t\tassign\tunused = w_r[(IW+BW-1):(AW+BW)];\n"
|
|
"\t\t// verilator lint_on UNUSED\n"
|
|
"\tend endgenerate\n"
|
|
"\n"
|
"endmodule\n");
|
"endmodule\n");
|
|
|
fclose(fp);
|
fclose(fp);
|
}
|
}
|
|
|
| Line 1274... |
Line 1291... |
"// fails the integration bench test (fft_tb).\n"
|
"// fails the integration bench test (fft_tb).\n"
|
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", prjname, creator);
|
"//\n", prjname, creator);
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"\n\n"
|
"\n\n"
|
"//\n"
|
"//\n"
|
"// How do we do bit reversing at two smples per clock? Can we separate out\n"
|
"// How do we do bit reversing at two smples per clock? Can we separate out\n"
|
"// our work into eight memory banks, writing two banks at once and reading\n"
|
"// our work into eight memory banks, writing two banks at once and reading\n"
|
| Line 1477... |
Line 1495... |
"// any reset signal.\n"
|
"// any reset signal.\n"
|
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", prjname, creator);
|
"//\n", prjname, creator);
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
|
|
fprintf(fp,
|
fprintf(fp,
|
"module\tbutterfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
|
"module\tbutterfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
|
"\t\to_left, o_right, o_aux);\n"
|
"\t\to_left, o_right, o_aux);\n"
|
"\t// Public changeable parameters ...\n"
|
"\t// Public changeable parameters ...\n"
|
| Line 1510... |
Line 1529... |
"\toutput\twire [(2*OWIDTH-1):0] o_left, o_right;\n"
|
"\toutput\twire [(2*OWIDTH-1):0] o_left, o_right;\n"
|
"\toutput\treg\to_aux;\n"
|
"\toutput\treg\to_aux;\n"
|
"\n", lgdelay(16,xtracbits), bflydelay(16, xtracbits),
|
"\n", lgdelay(16,xtracbits), bflydelay(16, xtracbits),
|
lgdelay(16,xtracbits));
|
lgdelay(16,xtracbits));
|
fprintf(fp,
|
fprintf(fp,
|
"\twire\t[(OWIDTH-1):0] o_left_r, o_left_i, o_right_r, o_right_i;\n"
|
|
"\n"
|
|
"\treg\t[(2*IWIDTH-1):0]\tr_left, r_right;\n"
|
"\treg\t[(2*IWIDTH-1):0]\tr_left, r_right;\n"
|
"\treg\t\t\t\tr_aux, r_aux_2;\n"
|
|
"\treg\t[(2*CWIDTH-1):0]\tr_coef, r_coef_2;\n"
|
"\treg\t[(2*CWIDTH-1):0]\tr_coef, r_coef_2;\n"
|
"\twire\tsigned\t[(IWIDTH-1):0]\tr_left_r, r_left_i, r_right_r, r_right_i;\n"
|
"\twire\tsigned\t[(IWIDTH-1):0]\tr_left_r, r_left_i, r_right_r, r_right_i;\n"
|
"\tassign\tr_left_r = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_left_r = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_left_i = r_left[ (IWIDTH-1):0];\n"
|
"\tassign\tr_left_i = r_left[ (IWIDTH-1):0];\n"
|
"\tassign\tr_right_r = r_right[(2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_right_r = r_right[(2*IWIDTH-1):(IWIDTH)];\n"
|
| Line 1658... |
Line 1674... |
"\treg\t\t[(2*IWIDTH+1):0] fifo_read;\n"
|
"\treg\t\t[(2*IWIDTH+1):0] fifo_read;\n"
|
"\tassign\tfifo_r = { {2{fifo_read[2*(IWIDTH+1)-1]}}, fifo_read[(2*(IWIDTH+1)-1):(IWIDTH+1)], {(CWIDTH-2){1\'b0}} };\n"
|
"\tassign\tfifo_r = { {2{fifo_read[2*(IWIDTH+1)-1]}}, fifo_read[(2*(IWIDTH+1)-1):(IWIDTH+1)], {(CWIDTH-2){1\'b0}} };\n"
|
"\tassign\tfifo_i = { {2{fifo_read[(IWIDTH+1)-1]}}, fifo_read[((IWIDTH+1)-1):0], {(CWIDTH-2){1\'b0}} };\n"
|
"\tassign\tfifo_i = { {2{fifo_read[(IWIDTH+1)-1]}}, fifo_read[((IWIDTH+1)-1):0], {(CWIDTH-2){1\'b0}} };\n"
|
"\n"
|
"\n"
|
"\n"
|
"\n"
|
"\treg\tsigned\t[(OWIDTH-1):0] b_left_r, b_left_i,\n"
|
|
"\t\t\t\t\t\tb_right_r, b_right_i;\n"
|
|
"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
|
"\treg\tsigned\t[(CWIDTH+IWIDTH+3-1):0] mpy_r, mpy_i;\n"
|
"\n");
|
"\n");
|
fprintf(fp,
|
fprintf(fp,
|
"\t// Let's do some rounding and remove unnecessary bits.\n"
|
"\t// Let's do some rounding and remove unnecessary bits.\n"
|
"\t// We have (IWIDTH+CWIDTH+3) bits here, we need to drop down to\n"
|
"\t// We have (IWIDTH+CWIDTH+3) bits here, we need to drop down to\n"
|
| Line 1717... |
Line 1731... |
"\t\t\t// although they only need to be (IWIDTH+1)\n"
|
"\t\t\t// although they only need to be (IWIDTH+1)\n"
|
"\t\t\t// + (CWIDTH) bits wide. (We\'ve got two\n"
|
"\t\t\t// + (CWIDTH) bits wide. (We\'ve got two\n"
|
"\t\t\t// extra bits we need to get rid of.)\n"
|
"\t\t\t// extra bits we need to get rid of.)\n"
|
"\t\t\tmpy_r <= p_one - p_two;\n"
|
"\t\t\tmpy_r <= p_one - p_two;\n"
|
"\t\t\tmpy_i <= p_three - p_one - p_two;\n"
|
"\t\t\tmpy_i <= p_three - p_one - p_two;\n"
|
"\n"
|
|
"\t\t\t// Second clock, round and latch for final clock\n"
|
|
"\t\t\tb_right_r <= rnd_right_r;\n"
|
|
"\t\t\tb_right_i <= rnd_right_i;\n"
|
|
"\t\t\tb_left_r <= rnd_left_r;\n"
|
|
"\t\t\tb_left_i <= rnd_left_i;\n"
|
|
"\t\tend\n"
|
"\t\tend\n"
|
"\n");
|
"\n");
|
|
|
fprintf(fp,
|
fprintf(fp,
|
"\treg\t[(AUXLEN-1):0]\taux_pipeline;\n"
|
"\treg\t[(AUXLEN-1):0]\taux_pipeline;\n"
|
| Line 1787... |
Line 1795... |
"//\n"
|
"//\n"
|
"// Project: %s\n"
|
"// Project: %s\n"
|
"//\n"
|
"//\n"
|
"// Purpose: This routine is identical to the butterfly.v routine found\n"
|
"// Purpose: This routine is identical to the butterfly.v routine found\n"
|
"// in 'butterfly.v', save only that it uses the verilog \n"
|
"// in 'butterfly.v', save only that it uses the verilog \n"
|
"// operator '*' in hopes that the synthesizer would be able\n"
|
"// operator '*' in hopes that the synthesizer would be able to optimize\n"
|
"// to optimize it with hardware resources.\n"
|
"// it with hardware resources.\n"
|
"//\n"
|
"//\n"
|
"// It is understood that a hardware multiply can complete its\n"
|
"// It is understood that a hardware multiply can complete its operation in\n"
|
"// operation in a single clock.\n"
|
"// a single clock.\n"
|
"//\n"
|
"//\n"
|
"//\n%s"
|
"//\n%s"
|
"//\n", prjname, creator);
|
"//\n", prjname, creator);
|
fprintf(fp, "%s", cpyleft);
|
fprintf(fp, "%s", cpyleft);
|
|
fprintf(fp, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fp,
|
fprintf(fp,
|
"module hwbfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
|
"module hwbfly(i_clk, i_rst, i_ce, i_coef, i_left, i_right, i_aux,\n"
|
"\t\to_left, o_right, o_aux);\n"
|
"\t\to_left, o_right, o_aux);\n"
|
"\t// Public changeable parameters ...\n"
|
"\t// Public changeable parameters ...\n"
|
"\tparameter IWIDTH=16,CWIDTH=IWIDTH+%d,OWIDTH=IWIDTH+1;\n"
|
"\tparameter IWIDTH=16,CWIDTH=IWIDTH+%d,OWIDTH=IWIDTH+1;\n"
|
| Line 1811... |
Line 1820... |
"\tinput\t\ti_aux;\n"
|
"\tinput\t\ti_aux;\n"
|
"\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
|
"\toutput\twire\t[(2*OWIDTH-1):0]\to_left, o_right;\n"
|
"\toutput\treg\to_aux;\n"
|
"\toutput\treg\to_aux;\n"
|
"\n", xtracbits);
|
"\n", xtracbits);
|
fprintf(fp,
|
fprintf(fp,
|
"\twire\t[(OWIDTH-1):0] o_left_r, o_left_i, o_right_r, o_right_i;\n"
|
|
"\n"
|
|
"\treg\t[(2*IWIDTH-1):0] r_left, r_right;\n"
|
"\treg\t[(2*IWIDTH-1):0] r_left, r_right;\n"
|
"\treg\t r_aux, r_aux_2;\n"
|
"\treg\t r_aux, r_aux_2;\n"
|
"\treg\t[(2*CWIDTH-1):0] r_coef, r_coef_2;\n"
|
"\treg\t[(2*CWIDTH-1):0] r_coef;\n"
|
"\twire signed [(IWIDTH-1):0] r_left_r, r_left_i, r_right_r, r_right_i;\n"
|
"\twire signed [(IWIDTH-1):0] r_left_r, r_left_i, r_right_r, r_right_i;\n"
|
"\tassign\tr_left_r = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_left_r = r_left[ (2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_left_i = r_left[ (IWIDTH-1):0];\n"
|
"\tassign\tr_left_i = r_left[ (IWIDTH-1):0];\n"
|
"\tassign\tr_right_r = r_right[(2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_right_r = r_right[(2*IWIDTH-1):(IWIDTH)];\n"
|
"\tassign\tr_right_i = r_right[(IWIDTH-1):0];\n"
|
"\tassign\tr_right_i = r_right[(IWIDTH-1):0];\n"
|
| Line 2027... |
Line 2034... |
"// FFT, there shall be (N-1) of these stages. \n"
|
"// FFT, there shall be (N-1) of these stages. \n"
|
"//\n%s"
|
"//\n%s"
|
"//\n",
|
"//\n",
|
(inv)?"i":"", (odd)?'o':'e', stage*2, (dbg)?"_dbg":"", prjname, creator);
|
(inv)?"i":"", (odd)?'o':'e', stage*2, (dbg)?"_dbg":"", prjname, creator);
|
fprintf(fstage, "%s", cpyleft);
|
fprintf(fstage, "%s", cpyleft);
|
|
fprintf(fstage, "//\n//\n`default_nettype\tnone\n//\n");
|
fprintf(fstage, "module\t%sfftstage_%c%d%s(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync%s);\n",
|
fprintf(fstage, "module\t%sfftstage_%c%d%s(i_clk, i_rst, i_ce, i_sync, i_data, o_data, o_sync%s);\n",
|
(inv)?"i":"", (odd)?'o':'e', stage*2, (dbg)?"_dbg":"",
|
(inv)?"i":"", (odd)?'o':'e', stage*2, (dbg)?"_dbg":"",
|
(dbg)?", o_dbg":"");
|
(dbg)?", o_dbg":"");
|
// These parameter values are useless at this point--they are to be
|
// These parameter values are useless at this point--they are to be
|
// replaced by the parameter values in the calling program. Only
|
// replaced by the parameter values in the calling program. Only
|
| Line 2138... |
Line 2146... |
"\t\tif (i_rst)\n"
|
"\t\tif (i_rst)\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
"\t\t\twait_for_sync <= 1\'b1;\n"
|
"\t\t\twait_for_sync <= 1\'b1;\n"
|
"\t\t\tiaddr <= 0;\n"
|
"\t\t\tiaddr <= 0;\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"\t\telse if ((i_ce)&&((~wait_for_sync)||(i_sync)))\n"
|
"\t\telse if ((i_ce)&&((!wait_for_sync)||(i_sync)))\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
"\t\t\t//\n"
|
"\t\t\t//\n"
|
"\t\t\t// First step: Record what we\'re not ready to use yet\n"
|
"\t\t\t// First step: Record what we\'re not ready to use yet\n"
|
"\t\t\t//\n"
|
"\t\t\t//\n"
|
"\t\t\tiaddr <= iaddr + { {(LGWIDTH-2){1\'b0}}, 1\'b1 };\n"
|
"\t\t\tiaddr <= iaddr + { {(LGWIDTH-2){1\'b0}}, 1\'b1 };\n"
|
"\t\t\twait_for_sync <= 1\'b0;\n"
|
"\t\t\twait_for_sync <= 1\'b0;\n"
|
"\t\tend\n"
|
"\t\tend\n"
|
"\talways @(posedge i_clk) // Need to make certain here that we don\'t read\n"
|
"\talways @(posedge i_clk) // Need to make certain here that we don\'t read\n"
|
"\t\tif ((i_ce)&&(~iaddr[LGSPAN])) // and write the same address on\n"
|
"\t\tif ((i_ce)&&(!iaddr[LGSPAN])) // and write the same address on\n"
|
"\t\t\timem[iaddr[(LGSPAN-1):0]] <= i_data; // the same clk\n"
|
"\t\t\timem[iaddr[(LGSPAN-1):0]] <= i_data; // the same clk\n"
|
"\n");
|
"\n");
|
|
|
fprintf(fstage,
|
fprintf(fstage,
|
"\t//\n"
|
"\t//\n"
|
| Line 2207... |
Line 2215... |
"\t\t\toB <= 0;\n"
|
"\t\t\toB <= 0;\n"
|
"\t\t\to_sync <= 0;\n"
|
"\t\t\to_sync <= 0;\n"
|
"\t\t\tb_started <= 0;\n"
|
"\t\t\tb_started <= 0;\n"
|
"\t\tend else if (i_ce)\n"
|
"\t\tend else if (i_ce)\n"
|
"\t\tbegin\n"
|
"\t\tbegin\n"
|
"\t\t\to_sync <= (~oB[LGSPAN])?ob_sync : 1\'b0;\n"
|
"\t\t\to_sync <= (!oB[LGSPAN])?ob_sync : 1\'b0;\n"
|
"\t\t\tif (ob_sync||b_started)\n"
|
"\t\t\tif (ob_sync||b_started)\n"
|
"\t\t\t\toB <= oB + { {(LGSPAN){1\'b0}}, 1\'b1 };\n"
|
"\t\t\t\toB <= oB + { {(LGSPAN){1\'b0}}, 1\'b1 };\n"
|
"\t\t\tif ((ob_sync)&&(~oB[LGSPAN]))\n"
|
"\t\t\tif ((ob_sync)&&(!oB[LGSPAN]))\n"
|
"\t\t\t// A butterfly output is available\n"
|
"\t\t\t// A butterfly output is available\n"
|
"\t\t\t\tb_started <= 1\'b1;\n"
|
"\t\t\t\tb_started <= 1\'b1;\n"
|
"\t\tend\n\n");
|
"\t\tend\n\n");
|
fprintf(fstage,
|
fprintf(fstage,
|
"\treg [(LGSPAN-1):0]\t\tdly_addr;\n"
|
"\treg [(LGSPAN-1):0]\t\tdly_addr;\n"
|
| Line 2230... |
Line 2238... |
"\t\t\tomem[dly_addr] <= dly_value;\n"
|
"\t\t\tomem[dly_addr] <= dly_value;\n"
|
"\n");
|
"\n");
|
fprintf(fstage,
|
fprintf(fstage,
|
"\talways @(posedge i_clk)\n"
|
"\talways @(posedge i_clk)\n"
|
"\t\tif (i_ce)\n"
|
"\t\tif (i_ce)\n"
|
"\t\t\to_data <= (~oB[LGSPAN])?ob_a : omem[oB[(LGSPAN-1):0]];\n"
|
"\t\t\to_data <= (!oB[LGSPAN])?ob_a : omem[oB[(LGSPAN-1):0]];\n"
|
"\n");
|
"\n");
|
fprintf(fstage, "endmodule\n");
|
fprintf(fstage, "endmodule\n");
|
}
|
}
|
|
|
void usage(void) {
|
void usage(void) {
|
| Line 2692... |
Line 2700... |
fprintf(vmain, "//\t\t%% %s\n", cmdline.c_str());
|
fprintf(vmain, "//\t\t%% %s\n", cmdline.c_str());
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "%s", creator);
|
fprintf(vmain, "%s", creator);
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "%s", cpyleft);
|
fprintf(vmain, "%s", cpyleft);
|
|
fprintf(vmain, "//\n//\n`default_nettype\tnone\n//\n");
|
|
|
|
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "//\n");
|
fprintf(vmain, "module %sfftmain(i_clk, i_rst, i_ce,\n", (inverse)?"i":"");
|
fprintf(vmain, "module %sfftmain(i_clk, i_rst, i_ce,\n", (inverse)?"i":"");
|
| Line 2727... |
Line 2736... |
fprintf(vmain, "\t\telse if (i_ce)\n");
|
fprintf(vmain, "\t\telse if (i_ce)\n");
|
fprintf(vmain, "\t\t\tbr_start <= 1\'b1;\n");
|
fprintf(vmain, "\t\t\tbr_start <= 1\'b1;\n");
|
}
|
}
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_rst, i_ce,\n");
|
fprintf(vmain, "\tdblstage\t#(IWIDTH)\tstage_2(i_clk, i_rst, i_ce,\n");
|
fprintf(vmain, "\t\t\t(~i_rst), i_left, i_right, br_left, br_right);\n");
|
fprintf(vmain, "\t\t\t(!i_rst), i_left, i_right, br_left, br_right);\n");
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
} else {
|
} else {
|
int nbits = nbitsin, dropbit=0;
|
int nbits = nbitsin, dropbit=0;
|
int obits = nbits+1+xtrapbits;
|
int obits = nbits+1+xtrapbits;
|
|
|
| Line 2747... |
Line 2756... |
mpystage = ((lgtmp-2) <= nummpy);
|
mpystage = ((lgtmp-2) <= nummpy);
|
|
|
if (mpystage)
|
if (mpystage)
|
fprintf(vmain, "\t// A hardware optimized FFT stage\n");
|
fprintf(vmain, "\t// A hardware optimized FFT stage\n");
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n", fftsize, fftsize);
|
fprintf(vmain, "\twire\t\tw_s%d;\n", fftsize);
|
|
fprintf(vmain, "\t// verilator lint_off UNUSED\n\twire\t\tw_os%d;\n\t// verilator lint_on UNUSED\n", fftsize);
|
fprintf(vmain, "\twire\t[%d:0]\tw_e%d, w_o%d;\n", 2*(obits+xtrapbits)-1, fftsize, fftsize);
|
fprintf(vmain, "\twire\t[%d:0]\tw_e%d, w_o%d;\n", 2*(obits+xtrapbits)-1, fftsize, fftsize);
|
fprintf(vmain, "\t%sfftstage_e%d%s\t#(IWIDTH,IWIDTH+%d,%d,%d,%d,%d,0)\tstage_e%d(i_clk, i_rst, i_ce,\n",
|
fprintf(vmain, "\t%sfftstage_e%d%s\t#(IWIDTH,IWIDTH+%d,%d,%d,%d,%d,0)\tstage_e%d(i_clk, i_rst, i_ce,\n",
|
(inverse)?"i":"", fftsize,
|
(inverse)?"i":"", fftsize,
|
((dbg)&&(dbgstage == fftsize))?"_dbg":"",
|
((dbg)&&(dbgstage == fftsize))?"_dbg":"",
|
xtracbits, obits+xtrapbits,
|
xtracbits, obits+xtrapbits,
|
lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
|
lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
|
fftsize);
|
fftsize);
|
fprintf(vmain, "\t\t\t(~i_rst), i_left, w_e%d, w_s%d%s);\n", fftsize, fftsize, ((dbg)&&(dbgstage == fftsize))?", o_dbg":"");
|
fprintf(vmain, "\t\t\t(!i_rst), i_left, w_e%d, w_s%d%s);\n", fftsize, fftsize, ((dbg)&&(dbgstage == fftsize))?", o_dbg":"");
|
fprintf(vmain, "\t%sfftstage_o%d\t#(IWIDTH,IWIDTH+%d,%d,%d,%d,%d,0)\tstage_o%d(i_clk, i_rst, i_ce,\n",
|
fprintf(vmain, "\t%sfftstage_o%d\t#(IWIDTH,IWIDTH+%d,%d,%d,%d,%d,0)\tstage_o%d(i_clk, i_rst, i_ce,\n",
|
(inverse)?"i":"", fftsize,
|
(inverse)?"i":"", fftsize,
|
xtracbits, obits+xtrapbits,
|
xtracbits, obits+xtrapbits,
|
lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
|
lgsize, lgtmp-2, lgdelay(nbits,xtracbits),
|
fftsize);
|
fftsize);
|
fprintf(vmain, "\t\t\t(~i_rst), i_right, w_o%d, w_os%d);\n", fftsize, fftsize);
|
fprintf(vmain, "\t\t\t(!i_rst), i_right, w_o%d, w_os%d);\n", fftsize, fftsize);
|
fprintf(vmain, "\n\n");
|
fprintf(vmain, "\n\n");
|
|
|
|
|
std::string fname;
|
std::string fname;
|
char numstr[12];
|
char numstr[12];
|
| Line 2804... |
Line 2814... |
|
|
mpystage = ((lgtmp-2) <= nummpy);
|
mpystage = ((lgtmp-2) <= nummpy);
|
|
|
if (mpystage)
|
if (mpystage)
|
fprintf(vmain, "\t// A hardware optimized FFT stage\n");
|
fprintf(vmain, "\t// A hardware optimized FFT stage\n");
|
fprintf(vmain, "\twire\t\tw_s%d, w_os%d;\n",
|
fprintf(vmain, "\twire\t\tw_s%d;\n",
|
tmp_size, tmp_size);
|
tmp_size);
|
|
fprintf(vmain, "\t// verilator lint_off UNUSED\n\twire\t\tw_os%d;\n\t// verilator lint_on UNUSED\n",
|
|
tmp_size);
|
fprintf(vmain,"\twire\t[%d:0]\tw_e%d, w_o%d;\n",
|
fprintf(vmain,"\twire\t[%d:0]\tw_e%d, w_o%d;\n",
|
2*(obits+xtrapbits)-1,
|
2*(obits+xtrapbits)-1,
|
tmp_size, tmp_size);
|
tmp_size, tmp_size);
|
fprintf(vmain, "\t%sfftstage_e%d%s\t#(%d,%d,%d,%d,%d,%d,%d)\tstage_e%d(i_clk, i_rst, i_ce,\n",
|
fprintf(vmain, "\t%sfftstage_e%d%s\t#(%d,%d,%d,%d,%d,%d,%d)\tstage_e%d(i_clk, i_rst, i_ce,\n",
|
(inverse)?"i":"", tmp_size,
|
(inverse)?"i":"", tmp_size,
|
| Line 2874... |
Line 2886... |
obits = nbits+((dropbit)?0:1);
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obits = nbits+((dropbit)?0:1);
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|
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if ((maxbitsout > 0)&&(obits > maxbitsout))
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if ((maxbitsout > 0)&&(obits > maxbitsout))
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obits = maxbitsout;
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obits = maxbitsout;
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fprintf(vmain, "\twire\t\tw_s4, w_os4;\n");
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fprintf(vmain, "\twire\t\tw_s4;\n");
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fprintf(vmain, "\t// verilator lint_off UNUSED\n\twire\t\tw_os4;\n\t// verilator lint_on UNUSED\n");
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fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*(obits+xtrapbits)-1);
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fprintf(vmain, "\twire\t[%d:0]\tw_e4, w_o4;\n", 2*(obits+xtrapbits)-1);
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fprintf(vmain, "\tqtrstage%s\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
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fprintf(vmain, "\tqtrstage%s\t#(%d,%d,%d,0,%d,%d)\tstage_e4(i_clk, i_rst, i_ce,\n",
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((dbg)&&(dbgstage==4))?"_dbg":"",
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((dbg)&&(dbgstage==4))?"_dbg":"",
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nbits+xtrapbits, obits+xtrapbits, lgsize,
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nbits+xtrapbits, obits+xtrapbits, lgsize,
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(inverse)?1:0, (dropbit)?0:0);
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(inverse)?1:0, (dropbit)?0:0);
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