URL https://opencores.org/ocsvn/dds_synthesizer/dds_synthesizer/trunk

Subversion Repositories dds_synthesizer

[/] [dds_synthesizer/] [trunk/] [vhdl/] [dds_synthesizer.vhd] - Diff between revs 5 and 8

Rev 5	Rev 8
Line 87...	Line 87...
`process (clk_i, rst_i)`	`process (clk_i, rst_i)`
`begin`	`begin`
`if rst_i = '1' then`	`if rst_i = '1' then`
`ftw_accu <= (others => '0');`	`ftw_accu <= (others => '0');`
`phase <= (others => '0');`	`phase <= (others => '0');`
	`lut_out <= (others => '0');`
	`lut_out_delay <= (others => '0');`
	`lut_out_inv_delay <= (others => '0');`
	`quadrant_3_or_4_delay <= '0';`
	`quadrant_3_or_4_2delay <= '0';`
`elsif clk_i'event and clk_i = '1' then`	`elsif clk_i'event and clk_i = '1' then`
`ftw_accu <= conv_std_logic_vector(conv_integer(ftw_accu) + conv_integer(ftw_i), ftw_width);`	`ftw_accu <= ftw_accu + ftw_i;`
`phase <= conv_std_logic_vector(conv_integer(ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH)) + conv_integer(phase_i), PHASE_WIDTH);`	`phase <= ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH) + phase_i;`
`if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then`	`if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then`
`lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);`	`lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);`
`else`	`else`
`lut_out <= sine_lut(conv_integer(lut_in));`	`lut_out <= sine_lut(conv_integer(lut_in));`
`end if;`	`end if;`