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Subversion Repositories de1_olpcl2294_system

[/] [de1_olpcl2294_system/] [trunk/] [src/] [top.v] - Diff between revs 8 and 10

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Rev 8 Rev 10
Line 60... Line 60... 
  inout             sd_dat3,                //  SD Card Data 3
 
  inout             sd_dat3,                //  SD Card Data 3
 
  inout             sd_cmd,                 //  SD Card Command Signal
 
  inout             sd_cmd,                 //  SD Card Command Signal
 
  output            sd_clk,                 //  SD Card Clock
 
  output            sd_clk,                 //  SD Card Clock
 
  ////////////////////////  I2C     ////////////////////////////////
 
  ////////////////////////  I2C     ////////////////////////////////
 
  inout             i2c_sdat,               //  I2C Data
 
  inout             i2c_sdat,               //  I2C Data
 
  output            i2c_sclk,               //  I2C Clock
 
  inout             i2c_sclk,               //  I2C Clock
 
  ////////////////////////  PS2     ////////////////////////////////
 
  ////////////////////////  PS2     ////////////////////////////////
 
  input             ps2_dat,                //  PS2 Data
 
  input             ps2_dat,                //  PS2 Data
 
  input             ps2_clk,                //  PS2 Clock
 
  input             ps2_clk,                //  PS2 Clock
 
  ////////////////////  USB JTAG link   ////////////////////////////
 
  ////////////////////  USB JTAG link   ////////////////////////////
 
  input             tdi,                    // CPLD -> FPGA (data in)
 
  input             tdi,                    // CPLD -> FPGA (data in)
Line 94... Line 94... 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
  //---------------------------------------------------
 
  // system wires
 
  // system wires
 
        wire                            sys_rst;
 
        wire                            sys_rst;
 
        wire        sys_clk = clock_24[0];
 
//      wire sys_clk = clock_27[0];
 
 
 
        wire sys_clk;
 
 
 
        wire sys_audio_clk_en;
 
 
 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
 
 
  // pll
 
 
 
  qaz_pll
 
 
 
    i_qaz_pll
 
 
 
    (
 
 
 
      .clock_24(clock_24),               //  24 MHz
 
 
 
      .clock_27(clock_27),               //  27 MHz
 
 
 
      .clock_50(clock_50),               //  50 MHz
 
 
 
      .ext_clock(ext_clock),              //  External Clock
 
 
 
 
 
 
 
      .sys_audio_clk_en(sys_audio_clk_en),
 
 
 
 
 
 
 
      .aud_xck(aud_xck),
 
 
 
      .sys_clk(sys_clk)
 
 
 
    );
 
 
 
 
 
 
 
 
 
//   //---------------------------------------------------
 
//   //---------------------------------------------------
 
//   // sync reset
 
//   // audio clock
 
//   sync 
//   wire       CLK_18_4, outclk_sig;
 
//     i_sync_reset( 
 
 
//             .async_sig(~key[0]), 
//   PLL
 
//             .sync_out(sys_rst), 
//     u0(
 
//             .clk(sys_clk) 
//         .inclk0(clock_27[0]),
 
 
 
//         .c0(CLK_18_4)
 
//           );
 
//           );
 
//      
//      
 
 
//   clk_buffer clk_buffer_inst (
 
 
 
//      .ena ( sys_audio_clk_en ),
 
 
 
//      .inclk ( CLK_18_4 ),
 
 
 
//      .outclk ( outclk_sig )
 
 
 
//      );
 
 
 
//
 
 
 
//   assign  aud_xck =  outclk_sig;
 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
  //---------------------------------------------------
 
  // FLED
 
  // FLED
 
        reg [24:0] counter;
 
        reg [24:0] counter;
 
        wire [7:0]  fled;
 
        wire [7:0]  fled;
Line 356... Line 384... 
      .s3_stb_o(s3_stb_o),
 
      .s3_stb_o(s3_stb_o),
 
      .s3_ack_i(s3_ack_i),
 
      .s3_ack_i(s3_ack_i),
 
      .s3_err_i(s3_err_i),
 
      .s3_err_i(s3_err_i),
 
      .s3_rty_i(s3_rty_i),
 
      .s3_rty_i(s3_rty_i),
 
      // Slave 4 Interface
 
      // Slave 4 Interface
 
      .s4_data_i(32'h0000_0000),
 
      .s4_data_i(s4_data_i),
 
      .s4_ack_i(1'b0),
 
      .s4_data_o(s4_data_o),
 
      .s4_err_i(1'b0),
 
      .s4_addr_o(s4_addr_o),
 
      .s4_rty_i(1'b0),
 
      .s4_sel_o(s4_sel_o),
 
 
 
      .s4_we_o(s4_we_o),
 
 
 
      .s4_cyc_o(s4_cyc_o),
 
 
 
      .s4_stb_o(s4_stb_o),
 
 
 
      .s4_ack_i(s4_ack_i),
 
 
 
      .s4_err_i(s4_err_i),
 
 
 
      .s4_rty_i(s4_rty_i),
 
      // Slave 5 Interface
 
      // Slave 5 Interface
 
      .s5_data_i(32'h0000_0000),
 
      .s5_data_i(s5_data_i),
 
      .s5_ack_i(1'b0),
 
      .s5_data_o(s5_data_o),
 
      .s5_err_i(1'b0),
 
      .s5_addr_o(s5_addr_o),
 
      .s5_rty_i(1'b0),
 
      .s5_sel_o(s5_sel_o),
 
 
 
      .s5_we_o(s5_we_o),
 
 
 
      .s5_cyc_o(s5_cyc_o),
 
 
 
      .s5_stb_o(s5_stb_o),
 
 
 
      .s5_ack_i(s5_ack_i),
 
 
 
      .s5_err_i(s5_err_i),
 
 
 
      .s5_rty_i(s5_rty_i),
 
      // Slave 6 Interface
 
      // Slave 6 Interface
 
      .s6_data_i(32'h0000_0000),
 
      .s6_data_i(32'h0000_0000),
 
      .s6_ack_i(1'b0),
 
      .s6_ack_i(1'b0),
 
      .s6_err_i(1'b0),
 
      .s6_err_i(1'b0),
 
      .s6_rty_i(1'b0),
 
      .s6_rty_i(1'b0),
Line 534... Line 574... 
                  .ext_padoe_o(gpio_b_ext_padoe_o)
 
                  .ext_padoe_o(gpio_b_ext_padoe_o)
 
            );
 
            );
 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
  //---------------------------------------------------
 
  // GPIO b
 
  // qaz_system
 
  qaz_system
 
  qaz_system
 
    i_qaz_system(
 
    i_qaz_system(
 
                    .sys_data_i(s3_data_o),
 
                    .sys_data_i(s3_data_o),
 
                    .sys_data_o(s3_data_i),
 
                    .sys_data_o(s3_data_i),
 
                    .sys_addr_i(s3_addr_o),
 
                    .sys_addr_i(s3_addr_o),
Line 550... Line 590... 
                    .sys_err_o(s3_err_i),
 
                    .sys_err_o(s3_err_i),
 
                    .sys_rty_o(s3_rty_i),
 
                    .sys_rty_o(s3_rty_i),
 
 
 
 
 
                    .async_rst_i(~key[0]),
 
                    .async_rst_i(~key[0]),
 
 
 
 
 
 
 
                    .sys_audio_clk_en(sys_audio_clk_en),
 
 
 
 
 
                    .hex0(gpio_a_aux_i[6:0]),
 
                    .hex0(gpio_a_aux_i[6:0]),
 
                    .hex1(gpio_a_aux_i[14:8]),
 
                    .hex1(gpio_a_aux_i[14:8]),
 
                    .hex2(gpio_a_aux_i[22:16]),
 
                    .hex2(gpio_a_aux_i[22:16]),
 
                    .hex3(gpio_a_aux_i[30:24]),
 
                    .hex3(gpio_a_aux_i[30:24]),
 
 
 
 
 
                    .sys_clk_i(sys_clk),
 
                    .sys_clk_i(sys_clk),
 
                    .sys_rst_o(sys_rst)
 
                    .sys_rst_o(sys_rst)
 
                  );
 
                  );
 
 
 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
 
 
  // simple pic
 
 
 
  wire        int_o;
 
 
 
  wire [1:0]  irq;
 
 
 
 
 
 
 
  qaz_pic
 
 
 
    i_qaz_pic
 
 
 
    (
 
 
 
      .sys_data_i(s4_data_o),
 
 
 
      .sys_data_o(s4_data_i),
 
 
 
      .sys_addr_i(s4_addr_o),
 
 
 
      .sys_sel_i(s4_sel_o),
 
 
 
      .sys_we_i(s4_we_o),
 
 
 
      .sys_cyc_i(s4_cyc_o),
 
 
 
      .sys_stb_i(s4_stb_o),
 
 
 
      .sys_ack_o(s4_ack_i),
 
 
 
      .sys_err_o(s4_err_i),
 
 
 
      .sys_rty_o(s4_rty_i),
 
 
 
 
 
 
 
      .int_o(int_o),
 
 
 
      .irq(irq),
 
 
 
 
 
 
 
      .sys_clk_i(sys_clk),
 
 
 
      .sys_rst_i(sys_rst)
 
 
 
    );
 
 
 
 
 
 
 
  //---------------------------------------------------
 
 
 
  // i2c_master_top
 
 
 
  wire i2c_inta_o;
 
 
 
  wire scl_pad_i;
 
 
 
  wire scl_pad_o;
 
 
 
  wire scl_padoen_o;
 
 
 
  wire sda_pad_i;
 
 
 
  wire sda_pad_o;
 
 
 
  wire sda_padoen_o;
 
 
 
 
 
 
 
  // i2c data out
 
 
 
  wire [7:0] i2c_data_o;
 
 
 
 
 
 
 
  assign s5_data_i[7:0] = i2c_data_o;
 
 
 
  assign s5_data_i[15:8] = i2c_data_o;
 
 
 
  assign s5_data_i[23:16] = i2c_data_o;
 
 
 
  assign s5_data_i[31:24] = i2c_data_o;
 
 
 
 
 
 
 
  // i2c data in mux
 
 
 
  reg [7:0] i2c_data_i_mux;
 
 
 
 
 
 
 
  always @(*)
 
 
 
    case( s5_sel_o )
 
 
 
      4'b0001:  i2c_data_i_mux = s5_data_o[7:0];
 
 
 
      4'b0010:  i2c_data_i_mux = s5_data_o[15:8];
 
 
 
      4'b0100:  i2c_data_i_mux = s5_data_o[23:16];
 
 
 
      4'b1000:  i2c_data_i_mux = s5_data_o[31:24];
 
 
 
      default:  i2c_data_i_mux = s5_data_o[7:0];
 
 
 
    endcase
 
 
 
 
 
 
 
  // i2c bus error
 
 
 
  reg i2c_bus_error;
 
 
 
 
 
 
 
  always @(*)
 
 
 
    case( s5_sel_o )
 
 
 
      4'b0001:  i2c_bus_error = 1'b0;
 
 
 
      4'b0010:  i2c_bus_error = 1'b0;
 
 
 
      4'b0100:  i2c_bus_error = 1'b0;
 
 
 
      4'b1000:  i2c_bus_error = 1'b0;
 
 
 
      default:  i2c_bus_error = 1'b1;
 
 
 
    endcase
 
 
 
 
 
 
 
  // i2c_master_top
 
 
 
  assign s5_err_i = 1'b0;
 
 
 
  assign s5_rty_i = 1'b0;
 
 
 
 
 
 
 
  i2c_master_top
 
 
 
    i_i2c_master_top
 
 
 
    (
 
 
 
      // wishbone signals
 
 
 
      .wb_clk_i(sys_clk),     // master clock input
 
 
 
      .wb_rst_i(sys_rst),     // synchronous active high reset
 
 
 
      .arst_i(1'b1),       // asynchronous reset
 
 
 
      .wb_adr_i(s5_addr_o[2:0]),     // lower address bits
 
 
 
      .wb_dat_i(i2c_data_i_mux),     // databus input
 
 
 
      .wb_dat_o(i2c_data_o),     // databus output
 
 
 
      .wb_we_i(s5_we_o),      // write enable input
 
 
 
      .wb_stb_i(s5_stb_o),     // stobe/core select signal
 
 
 
      .wb_cyc_i(s5_cyc_o),     // valid bus cycle input
 
 
 
      .wb_ack_o(s5_ack_i),     // bus cycle acknowledge output
 
 
 
      .wb_inta_o(i2c_inta_o),    // interrupt request signal output
 
 
 
 
 
 
 
      // i2c clock line
 
 
 
      .scl_pad_i(scl_pad_i),       // SCL-line input
 
 
 
      .scl_pad_o(scl_pad_o),       // SCL-line output (always 1'b0)
 
 
 
      .scl_padoen_o(scl_padoen_o),    // SCL-line output enable (active low)
 
 
 
 
 
 
 
      // i2c data line
 
 
 
      .sda_pad_i(sda_pad_i),       // SDA-line input
 
 
 
      .sda_pad_o(sda_pad_o),       // SDA-line output (always 1'b0)
 
 
 
      .sda_padoen_o(sda_padoen_o)    // SDA-line output enable (active low)
 
 
 
      );
 
 
 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
 
 
  // i2s_to_wb_tx
 
 
 
  i2s_to_wb_tx i_i2s_to_wb_tx
 
 
 
  (
 
 
 
//     .i2s_data_i(i2s_data_i),
 
 
 
//     .i2s_data_o(i2s_data_o),
 
 
 
//     .i2s_addr_i(i2s_addr_i),
 
 
 
//     .i2s_sel_i(i2s_sel_i),
 
 
 
//     .i2s_we_i(i2s_we_i),
 
 
 
//     .i2s_cyc_i(i2s_cyc_i),
 
 
 
//     .i2s_stb_i(i2s_stb_i),
 
 
 
//     .i2s_ack_o(i2s_ack_o),
 
 
 
//     .i2s_err_o(i2s_err_o),
 
 
 
//     .i2s_rty_o(i2s_rty_o),
 
 
 
 
 
 
 
    .i2s_sck_i(aud_bclk),
 
 
 
    .i2s_ws_i(aud_daclrck),
 
 
 
    .i2s_sd_o(aud_dacdat),
 
 
 
 
 
 
 
    .i2s_clk_i(sys_clk),
 
 
 
    .i2s_rst_i(sys_rst)
 
 
 
  );
 
 
 
 
 
 
 
 
 
  //---------------------------------------------------
 
  //---------------------------------------------------
 
  // IO pads
 
  // IO pads
 
  genvar i;
 
  genvar i;
 
 
 
 
 
  // gpio a
 
  // gpio a
Line 581... Line 748... 
    begin: gpio_b_pads
 
    begin: gpio_b_pads
 
      assign gpio_b_io_buffer_o[i] = gpio_b_ext_padoe_o[i] ? gpio_b_ext_pad_o[i] : 1'bz;
 
      assign gpio_b_io_buffer_o[i] = gpio_b_ext_padoe_o[i] ? gpio_b_ext_pad_o[i] : 1'bz;
 
    end
 
    end
 
  endgenerate
 
  endgenerate
 
 
 
 
 
 
 
  // i2c
 
 
 
  assign i2c_sclk = scl_padoen_o ? 1'bz : scl_pad_o;
 
 
 
  assign i2c_sdat = sda_padoen_o ? 1'bz : sda_pad_o;
 
 
 
 
 
  //---------------------------------------------------
 
  //---------------------------------------------------
 
  // outputs
 
  // outputs
 
 
 
 
 
  //  Turn off all display
 
 
 
//   assign  hex0        =   7'h7f;
 
 
 
//   assign  hex1        =   7'h7f;
 
 
 
//   assign  hex2        =   7'h7f;
 
 
 
//   assign  hex3        =   7'h7f;
 
 
 
//   assign  ledg        =   8'hff;
 
 
 
//   assign  ledg        =   fled;
 
 
 
//   assign  ledr        =   10'h000;
 
 
 
 
 
 
 
  //  All inout port turn to tri-state
 
  //  All inout port turn to tri-state
 
  assign  dram_dq     =   16'hzzzz;
 
  assign  dram_dq     =   16'hzzzz;
 
  assign  fl_dq       =   8'hzz;
 
  assign  fl_dq       =   8'hzz;
 
//   assign  sram_dq     =   16'hzzzz;
 
 
 
  assign  sd_dat      =   1'bz;
 
  assign  sd_dat      =   1'bz;
 
  assign  i2c_sdat    =   1'bz;
 
//   assign  i2c_sdat    =   1'bz;
 
  assign  aud_adclrck =   1'bz;
 
//   assign  aud_adclrck =   1'bz;
 
  assign  aud_daclrck =   1'bz;
 
//   assign  aud_daclrck =   1'bz;
 
  assign  aud_bclk    =   1'bz;
 
//   assign  aud_bclk    =   1'bz;
 
//   assign  gpio_0      =   36'hzzzzzzzzz;
 
 
 
//   assign  gpio_1      =   36'hzzzzzzzzz;
 
 
 
 
 
 
 
  assign hex0             = gpio_a_io_buffer_o[6:0];
 
  assign hex0             = gpio_a_io_buffer_o[6:0];
 
  assign hex1             = gpio_a_io_buffer_o[14:8];
 
  assign hex1             = gpio_a_io_buffer_o[14:8];
 
  assign hex2             = gpio_a_io_buffer_o[22:16];
 
  assign hex2             = gpio_a_io_buffer_o[22:16];
 
  assign hex3             = gpio_a_io_buffer_o[30:24];
 
  assign hex3             = gpio_a_io_buffer_o[30:24];
Line 621... Line 779... 
  assign ledg             = gpio_b_io_buffer_o[7:0];
 
  assign ledg             = gpio_b_io_buffer_o[7:0];
 
  assign ledr             = gpio_b_io_buffer_o[17:8];
 
  assign ledr             = gpio_b_io_buffer_o[17:8];
 
  assign gpio_b_aux_i     = { 24'b0, fled } ;
 
  assign gpio_b_aux_i     = { 24'b0, fled } ;
 
  assign gpio_b_ext_pad_i = { key, sw, 18'b0 };
 
  assign gpio_b_ext_pad_i = { key, sw, 18'b0 };
 
 
 
 
 
  assign gpio_1[35]       = ~gpio_b_inta_o;
 
//   assign gpio_1[35]       = ~gpio_b_inta_o;
 
 
 
  assign gpio_1[35] = ~int_o;
 
 
 
  assign irq[0]     = ~gpio_b_inta_o;
 
 
 
//   assign irq[1]     = 1'b1;
 
 
 
  assign irq[1]     = ~i2c_inta_o;
 
 
 
 
 
 
 
  assign scl_pad_i = i2c_sclk;
 
 
 
  assign sda_pad_i = i2c_sdat;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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