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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
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-- 6.25MHz, 1MHz and 500kHz
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-- 6.25MHz, 1MHz and 500kHz
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-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
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-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
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-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
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-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
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-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
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-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
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-- 2011/08/11 v1.01.0026 [JD] reduced switch inputs to 7, to save digital pins to the strobe signal.
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--
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--
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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| Line 39... |
Line 40... |
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entity debounce_atlys_top is
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entity debounce_atlys_top is
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Port (
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Port (
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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gclk_i : in std_logic := 'X'; -- board clock input 100MHz
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--- input slide switches ---
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--- input slide switches ---
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sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
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sw_i : in std_logic_vector (6 downto 0); -- 7 input slide switches
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--- output LEDs ----
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--- output LEDs ----
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led_o : out std_logic_vector (7 downto 0); -- output leds
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led_o : out std_logic_vector (6 downto 0); -- 7 output leds
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--- debug outputs ---
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--- debug outputs ---
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strb_o : out std_logic; -- core strobe output
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dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
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dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
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);
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);
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end debounce_atlys_top;
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end debounce_atlys_top;
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architecture rtl of debounce_atlys_top is
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architecture rtl of debounce_atlys_top is
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--=============================================================================================
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--=============================================================================================
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-- Constants
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-- Constants
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--=============================================================================================
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--=============================================================================================
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-- debounce generics
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-- debounce generics
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constant N : integer := 8; -- 8 bits (8 switch inputs)
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constant N : integer := 7; -- 7 bits (7 switch inputs)
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constant CNT_VAL : integer := 5000; -- debounce period = 1000 * 10 ns (50 us)
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constant CNT_VAL : integer := 5000; -- debounce period = 1000 * 10 ns (50 us)
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--=============================================================================================
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--=============================================================================================
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-- Signals for internal operation
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-- Signals for internal operation
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--=============================================================================================
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--=============================================================================================
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--- switch debouncer signals ---
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--- switch debouncer signals ---
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signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
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signal sw_data : std_logic_vector (6 downto 0) := (others => '0'); -- debounced switch data
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signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
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signal sw_reg : std_logic_vector (6 downto 0) := (others => '0'); -- registered switch data
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signal sw_new : std_logic := '0';
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signal sw_new : std_logic := '0';
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-- debug output signals
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-- debug output signals
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signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
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signal leds_reg : std_logic_vector (6 downto 0) := (others => '0');
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signal dbg : std_logic_vector (15 downto 0) := (others => '0');
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signal dbg : std_logic_vector (15 downto 0) := (others => '0');
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begin
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begin
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|
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--=============================================================================================
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--=============================================================================================
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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| Line 103... |
Line 103... |
--=============================================================================================
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--=============================================================================================
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-- LED register update
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-- LED register update
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leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
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leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
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-- update debug register
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-- update debug register
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dbg_lo_proc: dbg(7 downto 0) <= sw_i; -- lower debug port has direct switch connections
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dbg_in_proc: dbg(6 downto 0) <= sw_i; -- lower debug port has direct switch connections
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dbg_hi_proc: dbg(15 downto 8) <= sw_data; -- upper debug port has debounced switch data
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dbg_out_proc: dbg(13 downto 7) <= sw_data; -- upper debug port has debounced switch data
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dbg_strb_proc: dbg(14) <= sw_new; -- monitor new data strobe
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--=============================================================================================
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--=============================================================================================
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-- OUTPUT LOGIC PROCESSES
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-- OUTPUT LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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| Line 117... |
Line 118... |
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--=============================================================================================
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--=============================================================================================
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-- DEBUG LOGIC PROCESSES
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-- DEBUG LOGIC PROCESSES
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--=============================================================================================
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--=============================================================================================
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-- connect the debug vector outputs
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-- connect the debug vector outputs
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strb_o_proc: strb_o <= sw_new; -- connect strobe debug out
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dbg_o_proc: dbg_o <= dbg; -- drive the logic analyzer port
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dbg_o_proc: dbg_o <= dbg; -- drive the logic analyzer port
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|
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end rtl;
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end rtl;
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No newline at end of file
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No newline at end of file
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