VHDL simulation was done in ISIM, after Place & Route, with default constraints, for the slowest Spartan-6 device.
VHDL simulation was done in ISIM, after Place & Route, with default constraints, for the slowest Spartan-6 device.
SILICON VERIFICATION
SILICON VERIFICATION
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Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board.
Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board.
LICENSING
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This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing.
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer.
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer.
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
