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[/] [deslxcore/] [trunk/] [rtl/] [des_round.vhd] - Diff between revs 2 and 3

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----------------------------------------------------------------------------------
 
-- Company: 
-- Copyright (c) 2013 Antonio de la Piedra
-- Engineer: 
 
-- 
-- This program is free software: you can redistribute it and/or modify
-- Create Date:    12:52:29 02/20/2013 
-- it under the terms of the GNU General Public License as published by
-- Design Name: 
-- the Free Software Foundation, either version 3 of the License, or
-- Module Name:    des_round - Behavioral 
-- (at your option) any later version.
-- Project Name: 
 
-- Target Devices: 
-- This program is distributed in the hope that it will be useful,
-- Tool versions: 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- Description: 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--
-- GNU General Public License for more details.
-- Dependencies: 
 
--
-- You should have received a copy of the GNU General Public License
-- Revision: 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
-- Revision 0.01 - File Created
 
-- Additional Comments: 
 
--
 
----------------------------------------------------------------------------------
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
 
 
-- Uncomment the following library declaration if using
 
-- arithmetic functions with Signed or Unsigned values
 
--use IEEE.NUMERIC_STD.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
 
-- any Xilinx primitives in this code.
 
--library UNISIM;
 
--use UNISIM.VComponents.all;
 
 
 
entity des_round is
entity des_round is
        port(clk : in std_logic;
        port(clk : in std_logic;
                  l_0 : in std_logic_vector(31 downto 0);
                  l_0 : in std_logic_vector(31 downto 0);
                  r_0 : in std_logic_vector(31 downto 0);
                  r_0 : in std_logic_vector(31 downto 0);
                  k_i : in std_logic_vector(47 downto 0);
                  k_i : in std_logic_vector(47 downto 0);
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        F_FUN_0 : f_fun port map (clk, r_0, k_i, f_out_s);
        F_FUN_0 : f_fun port map (clk, r_0, k_i, f_out_s);
 
 
        l_1 <= r_0;
        l_1 <= r_0;
        r_1 <= l_0 xor f_out_s;
        r_1 <= l_0 xor f_out_s;
 
 
--      DSP_XOR_0 : dsp_xor port map (clk, l_0, f_out_s, r_1);
 
 
 
end Behavioral;
end Behavioral;
 
 
 
 
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