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[/] [deslxcore/] [trunk/] [rtl/] [key_schedule.vhd] - Diff between revs 2 and 3

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----------------------------------------------------------------------------------
 
-- Company: 
-- Copyright (c) 2013 Antonio de la Piedra
-- Engineer: 
 
-- 
-- This program is free software: you can redistribute it and/or modify
-- Create Date:    19:18:16 02/20/2013 
-- it under the terms of the GNU General Public License as published by
-- Design Name: 
-- the Free Software Foundation, either version 3 of the License, or
-- Module Name:    key_schedule - Behavioral 
-- (at your option) any later version.
-- Project Name: 
 
-- Target Devices: 
-- This program is distributed in the hope that it will be useful,
-- Tool versions: 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- Description: 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--
-- GNU General Public License for more details.
-- Dependencies: 
 
--
-- You should have received a copy of the GNU General Public License
-- Revision: 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
-- Revision 0.01 - File Created
 
-- Additional Comments: 
 
--
 
----------------------------------------------------------------------------------
 
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
 
 
-- Uncomment the following library declaration if using
 
-- arithmetic functions with Signed or Unsigned values
 
--use IEEE.NUMERIC_STD.ALL;
 
 
 
-- Uncomment the following library declaration if instantiating
 
-- any Xilinx primitives in this code.
 
--library UNISIM;
 
--use UNISIM.VComponents.all;
 
 
 
entity key_schedule is
entity key_schedule is
        port(clk : in std_logic;
        port(clk : in std_logic;
                  rst : in std_logic;
                  rst : in std_logic;
                  mode : in std_logic; -- 0 encrypt, 1 decrypt
                  mode : in std_logic; -- 0 encrypt, 1 decrypt
             key : in std_logic_vector(55 downto 0);
             key : in std_logic_vector(55 downto 0);
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                elsif rising_edge(clk) then
                elsif rising_edge(clk) then
                        shift_s <= shift_s(14 downto 0) & shift_s(15);
                        shift_s <= shift_s(14 downto 0) & shift_s(15);
                end if;
                end if;
        end process;
        end process;
 
 
        -- XXX Podemos meter aqui un FF para retrasar la salida n ciclos.
 
 
 
        key_pre_s <= c_0_s & d_0_s;
        key_pre_s <= c_0_s & d_0_s;
 
 
        pr_delay: process(clk, mode, key_pre_s)
        pr_delay: process(clk, mode, key_pre_s)
        begin
        begin
                if rising_edge(clk) then
                if rising_edge(clk) then

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