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/////////////////////////////////////////////////////////////////////
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//// ////
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//// FPU ////
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//// Floating Point Unit (Double precision) ////
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//// ////
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//// Author: David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 David Lundgren ////
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//// davidklun@gmail.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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module fpu_div( clk, rst, enable, opa, opb, sign, mantissa_7,
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exponent_out);
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input clk;
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input rst;
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input enable;
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input [63:0] opa;
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input [63:0] opb;
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output sign;
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output [55:0] mantissa_7;
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output [11:0] exponent_out;
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parameter preset = 53;
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reg [53:0] dividend_reg;
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reg [53:0] divisor_reg;
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reg enable_reg;
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reg enable_reg_2;
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reg enable_reg_a;
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reg enable_reg_b;
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reg enable_reg_c;
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reg enable_reg_d;
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reg enable_reg_e;
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reg [5:0] dividend_shift;
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reg [5:0] dividend_shift_2;
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reg [5:0] divisor_shift;
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reg [5:0] divisor_shift_2;
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reg [5:0] count_out;
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reg [11:0] exponent_out;
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wire sign = opa[63] ^ opb[63];
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reg [51:0] mantissa_a;
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reg [51:0] mantissa_b;
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wire [10:0] expon_a = opa[62:52];
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wire [10:0] expon_b = opb[62:52];
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wire a_is_norm = |expon_a;
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wire b_is_norm = |expon_b;
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wire a_is_zero = !(|opa[62:0]);
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wire [11:0] exponent_a = { 1'b0, expon_a};
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wire [11:0] exponent_b = { 1'b0, expon_b};
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reg [51:0] dividend_a;
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reg [51:0] dividend_a_shifted;
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wire [52:0] dividend_denorm = { dividend_a_shifted, 1'b0};
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wire [53:0] dividend_1 = a_is_norm ? { 2'b01, dividend_a } : { 1'b0, dividend_denorm};
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reg [51:0] divisor_b;
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reg [51:0] divisor_b_shifted;
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wire [52:0] divisor_denorm = { divisor_b_shifted, 1'b0};
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wire [53:0] divisor_1 = b_is_norm ? { 2'b01, divisor_b } : { 1'b0, divisor_denorm};
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wire [5:0] count_index = count_out;
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wire count_nonzero = !(count_index == 0);
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reg [53:0] quotient;
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reg [53:0] quotient_out;
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reg [53:0] remainder;
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reg [53:0] remainder_out;
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reg remainder_msb;
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reg count_nonzero_reg;
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reg count_nonzero_reg_2;
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reg [11:0] expon_term;
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reg expon_uf_1;
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reg [11:0] expon_uf_term_1;
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reg [11:0] expon_final_1;
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reg [11:0] expon_final_2;
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reg [11:0] expon_shift_a;
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reg [11:0] expon_shift_b;
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reg expon_uf_2;
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reg [11:0] expon_uf_term_2;
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reg [11:0] expon_uf_term_3;
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reg expon_uf_gt_maxshift;
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reg [11:0] expon_uf_term_4;
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reg [11:0] expon_final_3;
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reg [11:0] expon_final_4;
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wire quotient_msb = quotient_out[53];
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reg expon_final_4_et0;
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reg expon_final_4_term;
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reg [11:0] expon_final_5;
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reg [51:0] mantissa_1;
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wire [51:0] mantissa_2 = quotient_out[52:1];
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wire [51:0] mantissa_3 = quotient_out[51:0];
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wire [51:0] mantissa_4 = quotient_msb ? mantissa_2 : mantissa_3;
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wire [51:0] mantissa_5 = (expon_final_4 == 1) ? mantissa_2 : mantissa_4;
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wire [51:0] mantissa_6 = expon_final_4_et0 ? mantissa_1 : mantissa_5;
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wire [107:0] remainder_a = { quotient_out[53:0] , remainder_msb, remainder_out[52:0]};
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reg [6:0] remainder_shift_term;
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reg [107:0] remainder_b;
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wire [55:0] remainder_1 = remainder_b[107:52];
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wire [55:0] remainder_2 = { quotient_out[0] , remainder_msb, remainder_out[52:0], 1'b0 };
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wire [55:0] remainder_3 = { remainder_msb , remainder_out[52:0], 2'b0 };
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wire [55:0] remainder_4 = quotient_msb ? remainder_2 : remainder_3;
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wire [55:0] remainder_5 = (expon_final_4 == 1) ? remainder_2 : remainder_4;
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wire [55:0] remainder_6 = expon_final_4_et0 ? remainder_1 : remainder_5;
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wire m_norm = |expon_final_5;
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wire rem_lsb = |remainder_6[54:0];
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wire [55:0] mantissa_7 = { 1'b0, m_norm, mantissa_6, remainder_6[55], rem_lsb };
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always @ (posedge clk)
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begin
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if (rst)
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exponent_out <= 0;
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else
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exponent_out <= a_is_zero ? 12'b0 : expon_final_5;
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end
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always @ (posedge clk)
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begin
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if (rst)
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count_out <= 0;
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else if (enable_reg)
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count_out <= preset;
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else if (count_nonzero)
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count_out <= count_out - 1;
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end
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always @ (posedge clk)
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begin
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if (rst) begin
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quotient_out <= 0;
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remainder_out <= 0;
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end
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else begin
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quotient_out <= quotient;
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remainder_out <= remainder;
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end
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end
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always @ (posedge clk)
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begin
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if (rst)
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quotient <= 0;
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else if (count_nonzero_reg)
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quotient[count_index] <= !(divisor_reg > dividend_reg);
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end
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always @ (posedge clk)
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begin
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if (rst) begin
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remainder <= 0;
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remainder_msb <= 0;
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end
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else if (!count_nonzero_reg & count_nonzero_reg_2) begin
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remainder <= dividend_reg;
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remainder_msb <= (divisor_reg > dividend_reg) ? 0 : 1;
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end
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end
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always @ (posedge clk)
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begin
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if (rst) begin
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dividend_reg <= 0;
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divisor_reg <= 0;
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end
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else if (enable_reg_e) begin
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dividend_reg <= dividend_1;
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divisor_reg <= divisor_1;
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end
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else if (count_nonzero_reg)
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dividend_reg <= (divisor_reg > dividend_reg) ? dividend_reg << 1 :
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(dividend_reg - divisor_reg) << 1;
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// divisor doesn't change for the divide
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end
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always @ (posedge clk)
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begin
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if (rst) begin
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expon_term <= 0;
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expon_uf_1 <= 0;
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expon_uf_term_1 <= 0;
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expon_final_1 <= 0;
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expon_final_2 <= 0;
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expon_shift_a <= 0;
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expon_shift_b <= 0;
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expon_uf_2 <= 0;
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expon_uf_term_2 <= 0;
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expon_uf_term_3 <= 0;
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expon_uf_gt_maxshift <= 0;
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expon_uf_term_4 <= 0;
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expon_final_3 <= 0;
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expon_final_4 <= 0;
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expon_final_4_et0 <= 0;
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expon_final_4_term <= 0;
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expon_final_5 <= 0;
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mantissa_a <= 0;
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mantissa_b <= 0;
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dividend_a <= 0;
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divisor_b <= 0;
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dividend_shift_2 <= 0;
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divisor_shift_2 <= 0;
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remainder_shift_term <= 0;
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remainder_b <= 0;
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dividend_a_shifted <= 0;
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divisor_b_shifted <= 0;
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mantissa_1 <= 0;
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end
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else if (enable_reg_2) begin
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expon_term <= exponent_a + 1023;
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expon_uf_1 <= exponent_b > expon_term;
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expon_uf_term_1 <= expon_uf_1 ? (exponent_b - expon_term) : 0;
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expon_final_1 <= expon_term - exponent_b;
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expon_final_2 <= expon_uf_1 ? 0 : expon_final_1;
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expon_shift_a <= a_is_norm ? 0 : dividend_shift_2;
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expon_shift_b <= b_is_norm ? 0 : divisor_shift_2;
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expon_uf_2 <= expon_shift_a > expon_final_2;
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expon_uf_term_2 <= expon_uf_2 ? (expon_shift_a - expon_final_2) : 0;
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expon_uf_term_3 <= expon_uf_term_2 + expon_uf_term_1;
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expon_uf_gt_maxshift <= (expon_uf_term_3 > 51);
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expon_uf_term_4 <= expon_uf_gt_maxshift ? 52 : expon_uf_term_3;
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expon_final_3 <= expon_uf_2 ? 0 : (expon_final_2 - expon_shift_a);
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expon_final_4 <= expon_final_3 + expon_shift_b;
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expon_final_4_et0 <= (expon_final_4 == 0);
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expon_final_4_term <= expon_final_4_et0 ? 0 : 1;
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expon_final_5 <= quotient_msb ? expon_final_4 : expon_final_4 - expon_final_4_term;
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mantissa_a <= opa[51:0];
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mantissa_b <= opb[51:0];
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dividend_a <= mantissa_a;
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divisor_b <= mantissa_b;
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dividend_shift_2 <= dividend_shift;
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divisor_shift_2 <= divisor_shift;
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remainder_shift_term <= 52 - expon_uf_term_4;
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remainder_b <= remainder_a << remainder_shift_term;
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dividend_a_shifted <= dividend_a << dividend_shift_2;
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divisor_b_shifted <= divisor_b << divisor_shift_2;
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mantissa_1 <= quotient_out[53:2] >> expon_uf_term_4;
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end
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end
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always @ (posedge clk)
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begin
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if (rst) begin
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count_nonzero_reg <= 0;
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count_nonzero_reg_2 <= 0;
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enable_reg <= 0;
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enable_reg_a <= 0;
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enable_reg_b <= 0;
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enable_reg_c <= 0;
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enable_reg_d <= 0;
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enable_reg_e <= 0;
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end
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else begin
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count_nonzero_reg <= count_nonzero;
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count_nonzero_reg_2 <= count_nonzero_reg;
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enable_reg <= enable_reg_e;
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enable_reg_a <= enable;
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enable_reg_b <= enable_reg_a;
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enable_reg_c <= enable_reg_b;
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enable_reg_d <= enable_reg_c;
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enable_reg_e <= enable_reg_d;
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end
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end
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always @ (posedge clk)
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begin
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if (rst)
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enable_reg_2 <= 0;
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else if (enable)
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enable_reg_2 <= 1;
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end
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always @(dividend_a)
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casex(dividend_a)
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52'b1???????????????????????????????????????????????????: dividend_shift <= 0;
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52'b01??????????????????????????????????????????????????: dividend_shift <= 1;
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52'b001?????????????????????????????????????????????????: dividend_shift <= 2;
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52'b0001????????????????????????????????????????????????: dividend_shift <= 3;
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52'b00001???????????????????????????????????????????????: dividend_shift <= 4;
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52'b000001??????????????????????????????????????????????: dividend_shift <= 5;
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52'b0000001?????????????????????????????????????????????: dividend_shift <= 6;
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52'b00000001????????????????????????????????????????????: dividend_shift <= 7;
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52'b000000001???????????????????????????????????????????: dividend_shift <= 8;
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52'b0000000001??????????????????????????????????????????: dividend_shift <= 9;
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52'b00000000001?????????????????????????????????????????: dividend_shift <= 10;
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52'b000000000001????????????????????????????????????????: dividend_shift <= 11;
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52'b0000000000001???????????????????????????????????????: dividend_shift <= 12;
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52'b00000000000001??????????????????????????????????????: dividend_shift <= 13;
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52'b000000000000001?????????????????????????????????????: dividend_shift <= 14;
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52'b0000000000000001????????????????????????????????????: dividend_shift <= 15;
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52'b00000000000000001???????????????????????????????????: dividend_shift <= 16;
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52'b000000000000000001??????????????????????????????????: dividend_shift <= 17;
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52'b0000000000000000001?????????????????????????????????: dividend_shift <= 18;
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52'b00000000000000000001????????????????????????????????: dividend_shift <= 19;
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52'b000000000000000000001???????????????????????????????: dividend_shift <= 20;
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52'b0000000000000000000001??????????????????????????????: dividend_shift <= 21;
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52'b00000000000000000000001?????????????????????????????: dividend_shift <= 22;
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52'b000000000000000000000001????????????????????????????: dividend_shift <= 23;
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52'b0000000000000000000000001???????????????????????????: dividend_shift <= 24;
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52'b00000000000000000000000001??????????????????????????: dividend_shift <= 25;
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52'b000000000000000000000000001?????????????????????????: dividend_shift <= 26;
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52'b0000000000000000000000000001????????????????????????: dividend_shift <= 27;
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52'b00000000000000000000000000001???????????????????????: dividend_shift <= 28;
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52'b000000000000000000000000000001??????????????????????: dividend_shift <= 29;
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52'b0000000000000000000000000000001?????????????????????: dividend_shift <= 30;
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52'b00000000000000000000000000000001????????????????????: dividend_shift <= 31;
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52'b000000000000000000000000000000001???????????????????: dividend_shift <= 32;
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52'b0000000000000000000000000000000001??????????????????: dividend_shift <= 33;
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52'b00000000000000000000000000000000001?????????????????: dividend_shift <= 34;
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52'b000000000000000000000000000000000001????????????????: dividend_shift <= 35;
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52'b0000000000000000000000000000000000001???????????????: dividend_shift <= 36;
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52'b00000000000000000000000000000000000001??????????????: dividend_shift <= 37;
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52'b000000000000000000000000000000000000001?????????????: dividend_shift <= 38;
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52'b0000000000000000000000000000000000000001????????????: dividend_shift <= 39;
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52'b00000000000000000000000000000000000000001???????????: dividend_shift <= 40;
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52'b000000000000000000000000000000000000000001??????????: dividend_shift <= 41;
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52'b0000000000000000000000000000000000000000001?????????: dividend_shift <= 42;
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52'b00000000000000000000000000000000000000000001????????: dividend_shift <= 43;
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52'b000000000000000000000000000000000000000000001???????: dividend_shift <= 44;
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52'b0000000000000000000000000000000000000000000001??????: dividend_shift <= 45;
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52'b00000000000000000000000000000000000000000000001?????: dividend_shift <= 46;
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52'b000000000000000000000000000000000000000000000001????: dividend_shift <= 47;
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52'b0000000000000000000000000000000000000000000000001???: dividend_shift <= 48;
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52'b00000000000000000000000000000000000000000000000001??: dividend_shift <= 49;
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52'b000000000000000000000000000000000000000000000000001?: dividend_shift <= 50;
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52'b0000000000000000000000000000000000000000000000000001: dividend_shift <= 51;
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52'b0000000000000000000000000000000000000000000000000000: dividend_shift <= 52;
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endcase
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always @(divisor_b)
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casex(divisor_b)
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52'b1???????????????????????????????????????????????????: divisor_shift <= 0;
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52'b01??????????????????????????????????????????????????: divisor_shift <= 1;
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52'b001?????????????????????????????????????????????????: divisor_shift <= 2;
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52'b0001????????????????????????????????????????????????: divisor_shift <= 3;
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52'b00001???????????????????????????????????????????????: divisor_shift <= 4;
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52'b000001??????????????????????????????????????????????: divisor_shift <= 5;
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52'b0000001?????????????????????????????????????????????: divisor_shift <= 6;
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52'b00000001????????????????????????????????????????????: divisor_shift <= 7;
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52'b000000001???????????????????????????????????????????: divisor_shift <= 8;
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52'b0000000001??????????????????????????????????????????: divisor_shift <= 9;
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52'b00000000001?????????????????????????????????????????: divisor_shift <= 10;
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52'b000000000001????????????????????????????????????????: divisor_shift <= 11;
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52'b0000000000001???????????????????????????????????????: divisor_shift <= 12;
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52'b00000000000001??????????????????????????????????????: divisor_shift <= 13;
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52'b000000000000001?????????????????????????????????????: divisor_shift <= 14;
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52'b0000000000000001????????????????????????????????????: divisor_shift <= 15;
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52'b00000000000000001???????????????????????????????????: divisor_shift <= 16;
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52'b000000000000000001??????????????????????????????????: divisor_shift <= 17;
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52'b0000000000000000001?????????????????????????????????: divisor_shift <= 18;
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52'b00000000000000000001????????????????????????????????: divisor_shift <= 19;
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52'b000000000000000000001???????????????????????????????: divisor_shift <= 20;
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52'b0000000000000000000001??????????????????????????????: divisor_shift <= 21;
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52'b00000000000000000000001?????????????????????????????: divisor_shift <= 22;
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52'b000000000000000000000001????????????????????????????: divisor_shift <= 23;
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52'b0000000000000000000000001???????????????????????????: divisor_shift <= 24;
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52'b00000000000000000000000001??????????????????????????: divisor_shift <= 25;
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52'b000000000000000000000000001?????????????????????????: divisor_shift <= 26;
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52'b0000000000000000000000000001????????????????????????: divisor_shift <= 27;
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52'b00000000000000000000000000001???????????????????????: divisor_shift <= 28;
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52'b000000000000000000000000000001??????????????????????: divisor_shift <= 29;
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|
52'b0000000000000000000000000000001?????????????????????: divisor_shift <= 30;
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|
52'b00000000000000000000000000000001????????????????????: divisor_shift <= 31;
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|
52'b000000000000000000000000000000001???????????????????: divisor_shift <= 32;
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|
52'b0000000000000000000000000000000001??????????????????: divisor_shift <= 33;
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|
52'b00000000000000000000000000000000001?????????????????: divisor_shift <= 34;
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52'b000000000000000000000000000000000001????????????????: divisor_shift <= 35;
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|
52'b0000000000000000000000000000000000001???????????????: divisor_shift <= 36;
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|
52'b00000000000000000000000000000000000001??????????????: divisor_shift <= 37;
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|
52'b000000000000000000000000000000000000001?????????????: divisor_shift <= 38;
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|
52'b0000000000000000000000000000000000000001????????????: divisor_shift <= 39;
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|
52'b00000000000000000000000000000000000000001???????????: divisor_shift <= 40;
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|
52'b000000000000000000000000000000000000000001??????????: divisor_shift <= 41;
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|
52'b0000000000000000000000000000000000000000001?????????: divisor_shift <= 42;
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|
52'b00000000000000000000000000000000000000000001????????: divisor_shift <= 43;
|
|
52'b000000000000000000000000000000000000000000001???????: divisor_shift <= 44;
|
|
52'b0000000000000000000000000000000000000000000001??????: divisor_shift <= 45;
|
|
52'b00000000000000000000000000000000000000000000001?????: divisor_shift <= 46;
|
|
52'b000000000000000000000000000000000000000000000001????: divisor_shift <= 47;
|
|
52'b0000000000000000000000000000000000000000000000001???: divisor_shift <= 48;
|
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52'b00000000000000000000000000000000000000000000000001??: divisor_shift <= 49;
|
|
52'b000000000000000000000000000000000000000000000000001?: divisor_shift <= 50;
|
|
52'b0000000000000000000000000000000000000000000000000001: divisor_shift <= 51;
|
|
52'b0000000000000000000000000000000000000000000000000000: divisor_shift <= 52;
|
|
|
|
endcase
|
|
|
|
endmodule
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No newline at end of file
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No newline at end of file
|
