| Line 36... |
Line 36... |
# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name TOP_LEVEL_ENTITY fpmult_top
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set_global_assignment -name TOP_LEVEL_ENTITY fpmult
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.0
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:02:41 JANUARY 28, 2011"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:02:41 JANUARY 28, 2011"
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set_global_assignment -name LAST_QUARTUS_VERSION 10.1
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set_global_assignment -name LAST_QUARTUS_VERSION 10.1
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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| Line 53... |
Line 53... |
set_global_assignment -name VHDL_FILE src/fpmult_stage0_comp.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stage0_comp.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stage0.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stage0.vhdl
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
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set_global_assignment -name VHDL_FILE src/fpmult.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_comp.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_comp.vhdl
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set_global_assignment -name BDF_FILE src/fpmult_top.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE src/SignalTap.stp
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set_global_assignment -name USE_SIGNALTAP_FILE src/SignalTap.stp
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set_location_assignment PIN_A13 -to GPIO_0[0]
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set_location_assignment PIN_A13 -to GPIO_0[0]
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set_location_assignment PIN_B13 -to GPIO_0[1]
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set_location_assignment PIN_B13 -to GPIO_0[1]
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set_location_assignment PIN_A14 -to GPIO_0[2]
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set_location_assignment PIN_A14 -to GPIO_0[2]
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| Line 340... |
Line 334... |
set_location_assignment PIN_Y7 -to SRAM_LB_N
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set_location_assignment PIN_Y7 -to SRAM_LB_N
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set_location_assignment PIN_T8 -to SRAM_OE_N
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set_location_assignment PIN_T8 -to SRAM_OE_N
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set_location_assignment PIN_W7 -to SRAM_UB_N
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set_location_assignment PIN_W7 -to SRAM_UB_N
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set_location_assignment PIN_AA10 -to SRAM_WE_N
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set_location_assignment PIN_AA10 -to SRAM_WE_N
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set_location_assignment PIN_AB15 -to FL_CE_N
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set_location_assignment PIN_AB15 -to FL_CE_N
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set_global_assignment -name SOURCE_FILE src/sp.spf
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set_global_assignment -name QIP_FILE src/sp.qip
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name MISC_FILE "D:/Work/VHDL/fpmult/fpmult.dpf"
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set_global_assignment -name MISC_FILE "D:/Work/VHDL/fpmult/fpmult.dpf"
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set_global_assignment -name VHDL_FILE src/fpmult_stage23_comp.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stage23_comp.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stage23.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stage23.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_generic.vhdl
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set_global_assignment -name VHDL_FILE src/fp_generic.vhdl
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set_global_assignment -name VHDL_FILE src/fp_generic.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stageN.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stageN.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stageN_comp.vhdl
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set_global_assignment -name VHDL_FILE src/fpmult_stageN_comp.vhdl
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set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "D:/Work/VHDL/encore/fpmult/sim" -section_id eda_simulation
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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No newline at end of file
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No newline at end of file
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