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[/] [encore/] [trunk/] [fpmult/] [src/] [fpmult.vhdl] - Diff between revs 4 and 5
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| Rev 4 |
Rev 5 |
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Line 53... |
fpmult_stage0_in.a<=a;
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fpmult_stage0_in.a<=a;
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fpmult_stage0_in.b<=b;
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fpmult_stage0_in.b<=b;
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stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
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stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
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fpmult_stageN_in_array(1).a<=fpmult_stage0_out.a;
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fpmult_stageN_in_array(1)<=fpmult_stage0_out;
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fpmult_stageN_in_array(1).b<=fpmult_stage0_out.b;
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fpmult_stageN_in_array(1).p_sign<=fpmult_stage0_out.p_sign;
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fpmult_stageN_in_array(1).p_exp<=fpmult_stage0_out.p_exp;
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fpmult_stageN_in_array(1).p_mantissa<=fpmult_stage0_out.p_mantissa;
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pipeline:for N in 22 downto 1 generate
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pipeline:for N in 22 downto 1 generate
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stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
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stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
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fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
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fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
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end generate pipeline;
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end generate pipeline;
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fpmult_stage23_in.a<=fpmult_stageN_out_array(22).a;
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fpmult_stage23_in<=fpmult_stageN_out_array(22);
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fpmult_stage23_in.p_sign<=fpmult_stageN_out_array(22).p_sign;
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fpmult_stage23_in.p_exp<=fpmult_stageN_out_array(22).p_exp;
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fpmult_stage23_in.p_mantissa<=fpmult_stageN_out_array(22).p_mantissa;
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stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
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stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
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p<=fpmult_stage23_out.p;
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p<=fpmult_stage23_out.p;
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