| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// File name "wb_bus_mon.v" ////
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//// File name "wb_bus_mon.v" ////
|
//// ////
|
//// ////
|
//// This file is part of the Ethernet IP core project ////
|
//// This file is part of the "PCI bridge" project ////
|
//// http://www.opencores.org/projects/ethmac/ ////
|
//// http://www.opencores.org/cores/pci/ ////
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//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Miha Dolenc (mihad@opencores.org) ////
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//// - mihad@opencores.org ////
|
|
//// - Miha Dolenc ////
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//// ////
|
//// ////
|
//// All additional information is available in the README.pdf ////
|
//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// file. ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2002 Authors ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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| Line 40... |
Line 41... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
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//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/10/09 13:16:51 tadejm
|
|
// Just back-up; not completed testbench and some testcases are not
|
|
// wotking properly yet.
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|
//
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Headers changed.
|
// Headers changed.
|
//
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//
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// Revision 1.1 2002/09/13 11:57:20 mohor
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// Revision 1.1 2002/09/13 11:57:20 mohor
|
// New testbench. Thanks to Tadej M - "The Spammer".
|
// New testbench. Thanks to Tadej M - "The Spammer".
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| Line 74... |
Line 79... |
STB_O,
|
STB_O,
|
WE_O,
|
WE_O,
|
TAG_I,
|
TAG_I,
|
TAG_O,
|
TAG_O,
|
CAB_O,
|
CAB_O,
|
|
check_CTI,
|
log_file_desc
|
log_file_desc
|
) ;
|
) ;
|
|
|
input CLK_I ;
|
input CLK_I ;
|
input RST_I ;
|
input RST_I ;
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| Line 92... |
Line 98... |
input STB_O ;
|
input STB_O ;
|
input WE_O ;
|
input WE_O ;
|
input [(`WB_TAG_WIDTH-1):0] TAG_I ;
|
input [(`WB_TAG_WIDTH-1):0] TAG_I ;
|
input [(`WB_TAG_WIDTH-1):0] TAG_O ;
|
input [(`WB_TAG_WIDTH-1):0] TAG_O ;
|
input CAB_O ;
|
input CAB_O ;
|
|
input check_CTI ;
|
input [31:0] log_file_desc ;
|
input [31:0] log_file_desc ;
|
|
|
always@(posedge CLK_I or posedge RST_I)
|
always@(posedge CLK_I)
|
begin
|
begin
|
if (RST_I)
|
if (RST_I !== 1'b0)
|
begin
|
begin
|
// when reset is applied, all control signals must be low
|
// when reset is applied, all control signals must be low
|
if (CYC_O)
|
if (CYC_O !== 1'b0)
|
begin
|
|
$display("*E (%0t) CYC_O active under reset", $time) ;
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;
|
|
end
|
|
if (STB_O)
|
|
begin
|
begin
|
$display("*E (%0t) STB_O active under reset", $time) ;
|
message_out("CYC_O active under reset") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;
|
|
end
|
end
|
/*if (ACK_I)
|
|
$display("ACK_I active under reset") ;*/
|
if (STB_O !== 1'b0)
|
if (ERR_I)
|
|
begin
|
begin
|
$display("*E (%0t) ERR_I active under reset", $time) ;
|
message_out("STB_O active under reset") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;
|
|
end
|
end
|
if (RTY_I)
|
|
|
if (ACK_I !== 1'b0)
|
|
message_out("ACK_I active under reset") ;
|
|
|
|
if (ERR_I !== 1'b0)
|
begin
|
begin
|
$display("*E (%0t) RTY_I active under reset", $time) ;
|
message_out("ERR_I active under reset") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;
|
|
end
|
end
|
if (CAB_O)
|
|
|
if (RTY_I !== 1'b0)
|
begin
|
begin
|
$display("*E (%0t) CAB_O active under reset", $time) ;
|
message_out("RTY_I active under reset") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;
|
|
end
|
end
|
|
|
end // reset
|
end // reset
|
else
|
else
|
if (~CYC_O)
|
if (CYC_O !== 1'b1)
|
begin
|
begin
|
// when cycle indicator is low, all control signals must be low
|
// when cycle indicator is low, all control signals must be low
|
if (STB_O)
|
if (STB_O !== 1'b0)
|
begin
|
|
$display("*E (%0t) STB_O active without CYC_O being active", $time) ;
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;
|
|
end
|
|
if (ACK_I)
|
|
begin
|
begin
|
$display("*E (%0t) ACK_I active without CYC_O being active", $time) ;
|
message_out("STB_O active without CYC_O being active") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;
|
|
end
|
end
|
if (ERR_I)
|
|
|
if (ACK_I !== 1'b0)
|
begin
|
begin
|
$display("*E (%0t) ERR_I active without CYC_O being active", $time) ;
|
message_out("ACK_I active without CYC_O being active") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;
|
|
end
|
end
|
if (RTY_I)
|
|
|
if (ERR_I !== 1'b0)
|
begin
|
begin
|
$display("*E (%0t) RTY_I active without CYC_O being active", $time) ;
|
message_out("ERR_I active without CYC_O being active") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;
|
|
end
|
end
|
if (CAB_O)
|
|
|
if (RTY_I !== 1'b0)
|
begin
|
begin
|
$display("*E (%0t) CAB_O active without CYC_O being active", $time) ;
|
message_out("RTY_I active without CYC_O being active") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;
|
|
end
|
end
|
|
|
end // ~CYC_O
|
end // ~CYC_O
|
end
|
end
|
|
|
reg [`WB_DATA_WIDTH-1:0] previous_data ;
|
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
|
|
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
|
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
|
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
|
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
|
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
|
|
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
|
reg previous_stb ;
|
reg previous_stb ;
|
reg previous_ack ;
|
reg previous_ack ;
|
reg previous_err ;
|
reg previous_err ;
|
reg previous_rty ;
|
reg previous_rty ;
|
reg previous_cyc ;
|
reg previous_cyc ;
|
reg can_change ;
|
reg previous_we ;
|
|
|
always@(posedge CLK_I or posedge RST_I)
|
always@(posedge CLK_I or posedge RST_I)
|
begin
|
begin
|
if (RST_I)
|
if (RST_I)
|
begin
|
begin
|
previous_stb <= 1'b0 ;
|
previous_stb <= 1'b0 ;
|
previous_ack <= 1'b0 ;
|
previous_ack <= 1'b0 ;
|
previous_err <= 1'b0 ;
|
previous_err <= 1'b0 ;
|
previous_rty <= 1'b0 ;
|
previous_rty <= 1'b0 ;
|
previous_cyc <= 1'b0 ;
|
previous_cyc <= 1'b0 ;
|
|
previous_tag <= 'd0 ;
|
|
previous_we <= 1'b0 ;
|
|
previous_data_o <= 0 ;
|
|
previous_data_i <= 0 ;
|
|
previous_address <= 0 ;
|
|
previous_sel <= 0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
previous_stb <= STB_O ;
|
previous_stb <= STB_O ;
|
previous_ack <= ACK_I ;
|
previous_ack <= ACK_I ;
|
previous_err <= ERR_I ;
|
previous_err <= ERR_I ;
|
previous_rty <= RTY_I ;
|
previous_rty <= RTY_I ;
|
previous_cyc <= CYC_O ;
|
previous_cyc <= CYC_O ;
|
|
previous_tag <= TAG_O ;
|
|
previous_we <= WE_O ;
|
|
previous_data_o <= DAT_O ;
|
|
previous_data_i <= DAT_I ;
|
|
previous_address <= ADDR_O ;
|
|
previous_sel <= SEL_O ;
|
end
|
end
|
end
|
end
|
|
|
// cycle monitor
|
// cycle monitor
|
always@(posedge CLK_I)
|
always@(posedge CLK_I)
|
|
begin:cycle_monitor_blk
|
|
reg master_can_change ;
|
|
reg slave_can_change ;
|
|
|
|
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
|
begin
|
begin
|
if (CYC_O && ~RST_I) // cycle in progress
|
// check for two control signals active at same edge
|
|
if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
|
begin
|
begin
|
if (STB_O)
|
message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
|
|
end
|
|
|
|
if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
|
begin
|
begin
|
// check for two control signals active at same edge
|
message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
|
if ( ACK_I && RTY_I )
|
end
|
|
|
|
if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
|
begin
|
begin
|
$display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;
|
message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;
|
|
end
|
end
|
if ( ACK_I && ERR_I )
|
|
|
if (previous_cyc === 1'b1)
|
|
begin
|
|
if (previous_stb === 1'b1)
|
begin
|
begin
|
$display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;
|
if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
|
$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;
|
master_can_change = 1'b1 ;
|
|
else
|
|
master_can_change = 1'b0 ;
|
end
|
end
|
if ( RTY_I && ERR_I )
|
else
|
begin
|
begin
|
$display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;
|
master_can_change = 1'b1 ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;
|
|
end
|
end
|
|
|
if ( can_change !== 1 )
|
if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
|
begin
|
begin
|
if ( ADDR_O !== previous_address )
|
if (previous_stb === 1'b1)
|
|
slave_can_change = 1'b1 ;
|
|
else
|
|
slave_can_change = 1'b0 ;
|
|
end
|
|
else
|
begin
|
begin
|
$display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;
|
slave_can_change = 1'b1 ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;
|
end
|
|
end
|
|
else
|
|
begin
|
|
master_can_change = 1'b1 ;
|
|
slave_can_change = 1'b1 ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
master_can_change = 1'b1 ;
|
|
slave_can_change = 1'b1 ;
|
end
|
end
|
|
|
if ( SEL_O !== previous_sel )
|
if (master_can_change !== 1'b1)
|
begin
|
begin
|
$display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
|
if (CYC_O !== previous_cyc)
|
$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
|
begin
|
|
message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
|
end
|
end
|
|
|
if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
|
if (STB_O !== previous_stb)
|
begin
|
begin
|
$display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
|
message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
|
|
end
|
end
|
|
|
|
if (TAG_O !== previous_tag)
|
|
begin
|
|
message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
|
end
|
end
|
|
|
if ( ACK_I || RTY_I || ERR_I )
|
if (ADDR_O !== previous_address)
|
can_change = 1 ;
|
|
else
|
|
begin
|
begin
|
previous_data = DAT_O ;
|
message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
|
previous_address = ADDR_O ;
|
|
previous_sel = SEL_O ;
|
|
can_change = 0 ;
|
|
end
|
end
|
|
|
end // STB_O
|
if (SEL_O !== previous_sel)
|
else
|
|
begin //~STB_O
|
|
// while STB_O is inactive, only ACK_I is allowed to be active
|
|
if ( ERR_I )
|
|
begin
|
begin
|
$display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;
|
message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;
|
|
end
|
end
|
if ( RTY_I )
|
|
|
if (WE_O !== previous_we)
|
begin
|
begin
|
$display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;
|
message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;
|
|
end
|
end
|
|
|
if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
|
if (WE_O !== 1'b0)
|
begin
|
begin
|
$display("STB_O de-asserted without reception of slave response") ;
|
if (DAT_O !== previous_data_o)
|
$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
|
begin
|
|
message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
|
|
end
|
|
end
|
end
|
end
|
|
|
can_change = 1 ;
|
if (slave_can_change !== 1'b1)
|
end // ~STB_O
|
|
end // cycle in progress
|
|
else if (!RST_I)
|
|
begin
|
begin
|
// cycle not in progress anymore
|
if (previous_ack !== ACK_I)
|
can_change = 1 ;
|
|
if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
|
|
begin
|
begin
|
$display("STB_O de-asserted without reception of slave response") ;
|
message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
|
$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
|
end
|
|
|
|
if (previous_rty !== RTY_I)
|
|
begin
|
|
message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
|
|
end
|
|
|
|
if (previous_err !== ERR_I)
|
|
begin
|
|
message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
|
|
end
|
|
|
|
if (previous_data_i !== DAT_I)
|
|
begin
|
|
message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
|
end
|
end
|
end
|
end
|
end // cycle monitor
|
end // cycle monitor
|
|
|
// CAB_O monitor - CAB_O musn't change during one cycle
|
// CAB_O monitor - CAB_O musn't change during one cycle
|
| Line 293... |
Line 341... |
// cycle in progress - is this first clock edge in a cycle ?
|
// cycle in progress - is this first clock edge in a cycle ?
|
if (first_cab_val[1] === 1'b0)
|
if (first_cab_val[1] === 1'b0)
|
first_cab_val <= {1'b1, CAB_O} ;
|
first_cab_val <= {1'b1, CAB_O} ;
|
else if ( first_cab_val[0] !== CAB_O )
|
else if ( first_cab_val[0] !== CAB_O )
|
begin
|
begin
|
$display("*E (%0t) CAB_O value changed during cycle", $time) ;
|
$display("CAB_O value changed during cycle") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;
|
$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
|
end
|
end
|
end
|
end
|
end // CAB_O monitor
|
end // CAB_O monitor
|
|
|
|
// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
|
|
reg [2:0] first_cti_val ;
|
|
always@(posedge CLK_I or posedge RST_I)
|
|
begin
|
|
if (RST_I)
|
|
first_cti_val <= 3'b000 ;
|
|
// logging for burst cycle
|
|
else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
|
|
begin
|
|
message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
|
|
$display("CTI_O didn't change to '111' when end of burst") ;
|
|
$fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
|
|
first_cti_val <= 3'b000 ;
|
|
end
|
|
else if (CYC_O === 0)
|
|
first_cti_val <= 3'b000 ;
|
|
else
|
|
begin
|
|
if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
|
|
first_cti_val <= 3'b001 ;
|
|
else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
|
|
first_cti_val <= 3'b010 ;
|
|
else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
|
|
first_cti_val <= 3'b011 ;
|
|
else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
|
|
first_cti_val <= 3'b010 ;
|
|
// logging for clasic cycles
|
|
else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
|
|
begin
|
|
message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
|
|
$display("CTI_O change during CYC_O when clasic cycle") ;
|
|
$fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
|
|
end
|
|
// logging for end of burs cycle
|
|
else if (check_CTI && (first_cti_val == 3'b010))
|
|
begin
|
|
message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
|
|
$display("CTI_O change to '111' before end of burst") ;
|
|
$fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
|
|
end
|
|
end
|
|
end
|
|
|
// WE_O monitor for consecutive address bursts
|
// WE_O monitor for consecutive address bursts
|
reg [1:0] first_we_val ;
|
reg [1:0] first_we_val ;
|
always@(posedge CLK_I or posedge RST_I)
|
always@(posedge CLK_I or posedge RST_I)
|
begin
|
begin
|
if (~CYC_O || ~CAB_O || RST_I)
|
if (~CYC_O || ~CAB_O || RST_I)
|
| Line 313... |
Line 404... |
// cycle in progress - is this first clock edge in a cycle ?
|
// cycle in progress - is this first clock edge in a cycle ?
|
if (first_we_val[1] == 1'b0)
|
if (first_we_val[1] == 1'b0)
|
first_we_val <= {1'b1, WE_O} ;
|
first_we_val <= {1'b1, WE_O} ;
|
else if ( first_we_val[0] != WE_O )
|
else if ( first_we_val[0] != WE_O )
|
begin
|
begin
|
$display("*E (%0t) WE_O value changed during CAB cycle", $time) ;
|
$display("WE_O value changed during CAB cycle") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;
|
$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
|
end
|
end
|
end
|
end
|
end // CAB_O monitor
|
end // CAB_O monitor
|
|
|
// address monitor for consecutive address bursts
|
// address monitor for consecutive address bursts
|
| Line 330... |
Line 421... |
else
|
else
|
begin
|
begin
|
if (STB_O && ACK_I)
|
if (STB_O && ACK_I)
|
begin
|
begin
|
if (address[`WB_ADDR_WIDTH] == 1'b0)
|
if (address[`WB_ADDR_WIDTH] == 1'b0)
|
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
|
begin
|
|
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
|
|
end
|
else
|
else
|
begin
|
begin
|
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
|
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
|
begin
|
begin
|
$display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;
|
$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;
|
message_out("Consecutive address burst address incrementing incorrect") ;
|
end
|
end
|
else
|
else
|
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
|
address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
|
end
|
end
|
end
|
end
|
end
|
end
|
end // address monitor
|
end // address monitor
|
|
|
// data monitor
|
// data monitor
|
always@(posedge CLK_I or posedge RST_I)
|
always@(posedge CLK_I or posedge RST_I)
|
|
begin:data_monitor_blk
|
|
reg last_valid_we ;
|
|
reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
|
|
|
|
if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
|
begin
|
begin
|
if (CYC_O && STB_O && ~RST_I)
|
if (STB_O !== 1'b0)
|
begin
|
begin
|
if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
|
last_valid_we = WE_O ;
|
|
last_valid_sel = SEL_O ;
|
|
|
|
if ( (ADDR_O ^ ADDR_O) !== 0 )
|
|
begin
|
|
message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
|
|
end
|
|
|
|
if ( (SEL_O ^ SEL_O) !== 0 )
|
begin
|
begin
|
$display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;
|
message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;
|
|
end
|
end
|
|
|
if ( WE_O )
|
if ( WE_O )
|
begin
|
begin
|
if (
|
if (
|
(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) ||
|
( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
|
(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) ||
|
( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
|
(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
|
( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
|
(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
|
( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
|
)
|
)
|
begin
|
begin
|
$display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;
|
message_out("Master provided invalid data during write and qualified it with STB_O") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;
|
$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
|
$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;
|
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;
|
end
|
end
|
end
|
|
|
|
if ((TAG_O ^ TAG_O) !== 0)
|
|
begin
|
|
message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
|
end
|
end
|
else
|
end
|
if (~WE_O && ACK_I)
|
|
|
if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
|
begin
|
begin
|
if (
|
if (
|
(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) ||
|
( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
|
(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) ||
|
( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
|
(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
|
( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
|
(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
|
( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
|
)
|
)
|
begin
|
begin
|
$display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;
|
message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;
|
$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
|
$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;
|
$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
|
else
|
|
begin
|
|
last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
|
|
last_valid_we = 1'bx ;
|
|
end
|
end
|
end
|
|
|
initial
|
task message_out ;
|
|
input [7999:0] message_i ;
|
begin
|
begin
|
previous_data = 0 ;
|
$display("Time: %t", $time) ;
|
previous_address = 0 ;
|
$display("%m, %0s", message_i) ;
|
can_change = 1 ;
|
$fdisplay(log_file_desc, "Time: %t", $time) ;
|
|
$fdisplay(log_file_desc, "%m, %0s", message_i) ;
|
end
|
end
|
|
endtask // display message
|
|
|
endmodule // BUS_MON
|
endmodule // BUS_MON
|
|
|
No newline at end of file
|
No newline at end of file
|
