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/* Synthesisable testbench/BiST for FIR Filter design.
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Copyright© 2012 Tauhop Solutions. All rights reserved.
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This core is free hardware design; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with this library; if not, write to the
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Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA.
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License: LGPL.
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@dependencies:
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@designer(s):
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Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] | [daniel.kho@sophicdesign.com.my];
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Tan Hooi Jing [hooijingtan@gmail.com]
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@info:
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Revision History: @see Mercurial log for full list of changes.
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This notice and disclaimer must be retained as part of this text at all times.
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*/
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity tb_fir is end entity tb_fir;
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entity tb_fir is generic(order:positive:=30; width:positive:=16);
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port(
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-- clk:in std_ulogic:='0';
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-- nRst:in std_ulogic:='0';
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--u:in signed(16-1 downto 0);
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y:out signed(16-1 downto 0)
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);
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end entity tb_fir;
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architecture sim of tb_fir is
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architecture rtl of tb_fir is
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signal clk,reset:std_ulogic:='0';
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signal reset:std_ulogic:='0';
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signal u: unsigned(16-1 downto 0);
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signal u:signed(16-1 downto 0);
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signal y: unsigned(16*2-1 downto 0);
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signal trig:std_logic;
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signal count: unsigned(3 downto 0);
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/* synthesis translate_off */
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signal clk:std_ulogic:='0';
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signal nRst:std_ulogic:='1';
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/* synthesis translate_on */
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signal count:unsigned(8 downto 0);
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signal pwrUpCnt:unsigned(3 downto 0):=(others=>'0');
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signal pwrUpCnt:unsigned(3 downto 0):=(others=>'0');
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/* on-chip debugger */
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signal dbgSignals:std_ulogic_vector(127 downto 0):=(others=>'0');
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/* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
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attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera:
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-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx:
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begin
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begin
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/* synthesis translate_off*/
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clk<=not clk after 10 ns;
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clk<=not clk after 10 ns;
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process(clk) is begin
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/* synthesis translate_on*/
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if pwrUpCnt<10 then reset<='1';
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process(pwrUpCnt,nRst) is begin
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if pwrUpCnt<10 or nRst='0' then reset<='1';
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else reset<='0';
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else reset<='0';
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end if;
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end if;
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end process;
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end process;
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fir_test: entity work.fir(rtl)
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process(reset,clk) is begin
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if reset='1' then count<=(others =>'0');
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elsif rising_edge(clk) then
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if count<300 then count<=count+1; end if;
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end if;
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end process;
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process(nRst,clk) is begin
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if nRst='0' then pwrUpCnt<=(others =>'0');
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elsif rising_edge(clk) then
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if pwrUpCnt<10 then pwrUpCnt<=pwrUpCnt+1; end if;
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end if;
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end process;
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/* Impulse generator for impulse response measurement. */
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u <= (0=>'1', others=>'0') when count=1 else (others=>'0');
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filter: entity work.fir(rtl)
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generic map(order=>order, width=>width)
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port map (
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port map (
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reset => reset,
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reset => reset,
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clk => clk,
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clk => clk,
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/* Filter ports. */
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/* Filter ports. */
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u => u,
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u => u,
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y => y
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y => y
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);
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);
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process(reset,clk) is begin
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if reset = '1' then count <= (others =>'0');
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elsif rising_edge(clk) then
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if count<10 then count<=count+1; end if;
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end if;
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end process;
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process(clk) is begin
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/* Simulation only. */
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/* synthesis translate_off */
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reporter: process(clk) is begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if pwrUpCnt<10 then pwrUpCnt<=pwrUpCnt+1; end if;
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/* (u,y) pairs will be exported to CSV and Matlab for plotting.
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Results are then correlated to digital simulations and Matlab
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simulations of the filter.
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*/
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report ";" & integer'image(to_integer(u)) & ";"
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& integer'image(to_integer(y));
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end if;
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end if;
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end process reporter;
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process is begin
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assert now<5 us report "simulation stopped." severity failure;
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wait;
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end process;
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end process;
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/* synthesis translate_on */
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u<= x"0001" when count=5 else x"0000";
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end architecture sim;
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/* Hardware debugger (SignalTap II embedded logic analyser). */
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trig<='1' when count<300 else '0'; -- Stop SignalTap Triggering after 300 counts, Total data=280
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/* SignalTap debugger. */
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dbgSignals(width-1 downto 0)<=std_ulogic_vector(u); -- u:16bits
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dbgSignals(width*2-1 downto width)<=std_ulogic_vector(y); -- y:32bits
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dbgSignals(8+width*2 downto width*2)<=std_ulogic_vector(count); --9bits (300<512)
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/* debugger: entity work.stp(syn) port map(
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acq_clk=>clk,
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acq_data_in=>std_logic_vector(dbgSignals), -- Type conversion: std_ulogic_vector --> std_logic_vector
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acq_trigger_in=>"1",
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trigger_in=>trig
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);
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*/
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end architecture rtl;
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