URL
https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk
Show entire file |
Details |
Blame |
View Log
Rev 15 |
Rev 17 |
Line 33... |
Line 33... |
# project name
|
# project name
|
PROJECT = fir_wishbone
|
PROJECT = fir_wishbone
|
|
|
ROOT_PATH = $(PWD)
|
ROOT_PATH = $(PWD)
|
MODEL_SRC_PATH = $(ROOT_PATH)/../model
|
MODEL_SRC_PATH = $(ROOT_PATH)/../model
|
#VHDL_SRC_PATH = $(ROOT_PATH)/../hw
|
VHDL_SRC_PATH = $(ROOT_PATH)/../hw
|
VHDL_SRC_PATH = $(ROOT_PATH)/../design
|
|
VHDL_TB_PATH = $(ROOT_PATH)/../tester
|
VHDL_TB_PATH = $(ROOT_PATH)/../tester
|
#COMMONFILES_PATH = $(SRC_PATH)/common
|
#COMMONFILES_PATH = $(SRC_PATH)/common
|
|
|
# model files
|
# model files
|
MODEL_FILES = $(SRC_PATH)/*.sagews $(SRC_PATH)/*.m $(SRC_PATH)/*.c
|
MODEL_FILES = $(SRC_PATH)/*.sagews $(SRC_PATH)/*.m $(SRC_PATH)/*.c
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.