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[/] [fir_wishbone/] [trunk/] [workspaces/] [synthesis/] [quartus/] [fir.qsf] - Diff between revs 8 and 16

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Rev 8 Rev 16
Line 36... Line 36...
# -------------------------------------------------------------------------- #
# -------------------------------------------------------------------------- #
 
 
 
 
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY tb_fir
set_global_assignment -name TOP_LEVEL_ENTITY fir
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:57:28  MARCH 05, 2014"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:57:28  MARCH 05, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl"
set_global_assignment -name VHDL_FILE "../../../hw/quartus-synthesis/fir.vhdl"
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl"
#set_global_assignment -name VHDL_FILE ../../../tester/tb_fir.vhdl
set_global_assignment -name VHDL_FILE ../../../tester/stp.vhd
set_global_assignment -name VHDL_FILE ./synthesis/quartus/stp/synthesis/stp.vhd
 
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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