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Subversion Repositories fpga-cf

[/] [fpga-cf/] [trunk/] [hdl/] [topv5_prototest.v] - Diff between revs 8 and 10

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Rev 8 Rev 10
Line 244... Line 244... 
wire ch5_out_dst_rdy;
 
wire ch5_out_dst_rdy;
 
wire [7:0] ch5_out_data;
 
wire [7:0] ch5_out_data;
 
wire ch5_wen;
 
wire ch5_wen;
 
wire ch5_ren;
 
wire ch5_ren;
 
 
 
 
 
 
 
wire ch5_in_sof_l;
 
 
 
wire ch5_in_eof_l;
 
 
 
wire ch5_in_src_rdy_l;
 
 
 
wire ch5_in_dst_rdy_l;
 
 
 
wire [7:0] ch5_in_data_l;
 
 
 
wire ch5_out_sof_l;
 
 
 
wire ch5_out_eof_l;
 
 
 
wire ch5_out_src_rdy_l;
 
 
 
wire ch5_out_dst_rdy_l;
 
 
 
wire [7:0] ch5_out_data_l;
 
 
 
wire ch5_wen_l;
 
 
 
wire ch5_ren_l;
 
 
 
 
 
wire ch6_in_sof;
 
wire ch6_in_sof;
 
wire ch6_in_eof;
 
wire ch6_in_eof;
 
wire ch6_in_src_rdy;
 
wire ch6_in_src_rdy;
 
wire ch6_in_dst_rdy;
 
wire ch6_in_dst_rdy;
 
wire [7:0] ch6_in_data;
 
wire [7:0] ch6_in_data;
Line 406... Line 419... 
//-------------------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------
 
//                                                       Sand Box Areas
 
//                                                       Sand Box Areas
 
//-------------------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------
 
 
 
 
 
port_sha1 pr_channel_5 (
 
port_md5 md5_channel_5 (
 
        .clk(clk_controlled),
 
        .clk(clk_controlled),
 
        .rst(rst_local),
 
        .rst(usr_rst),
 
        .wen ( 1 ),
 
        .wen ( 1 ),
 
        .ren ( 1 ),
 
        .ren ( 1 ),
 
        .in_data ( ch5_out_data_l ),    // Inport
 
        .in_data ( ch5_out_data_l ),    // Inport
 
        .in_sof ( ch5_out_sof_l ),      // Inport
 
        .in_sof ( ch5_out_sof_l ),      // Inport
 
        .in_eof ( ch5_out_eof_l ),      // Inport
 
        .in_eof ( ch5_out_eof_l ),      // Inport
Line 462... Line 475... 
        .out_src_rdy ( ch5_out_src_rdy_l ),     // Outport
 
        .out_src_rdy ( ch5_out_src_rdy_l ),     // Outport
 
        .in_dst_rdy ( ch5_out_dst_rdy ) // Inport
 
        .in_dst_rdy ( ch5_out_dst_rdy ) // Inport
 
);
 
);
 
 
 
 
 
 
 
 
 
port_sha1 pr_channel_6 (
 
port_sha1 sha1_channel_6 (
 
        .clk(clk_local),
 
        .clk(clk_local),
 
        .rst(rst_local),
 
        .rst(rst_local),
 
        .wen ( ch6_wen ),
 
        .wen ( ch6_wen ),
 
        .ren ( ch6_ren ),
 
        .ren ( ch6_ren ),
 
        .in_data ( ch6_out_data ),      // Inport
 
        .in_data ( ch6_out_data ),      // Inport

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