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-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: square-root entity for the square-root unit
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity sqrt is
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generic (RD_WIDTH: integer:=52; SQ_WIDTH: integer:=26); -- SQ_WIDTH = RD_WIDTH/2 (+ 1 if odd)
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port(
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clk_i : in std_logic;
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rad_i : in std_logic_vector(RD_WIDTH-1 downto 0); -- hidden(1) & fraction(23)
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start_i : in std_logic;
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ready_o : out std_logic;
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sqr_o : out std_logic_vector(SQ_WIDTH-1 downto 0);
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ine_o : out std_logic
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);
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end sqrt;
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architecture rtl of sqrt is
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signal s_rad_i: std_logic_vector(RD_WIDTH-1 downto 0);
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signal s_start_i, s_ready_o : std_logic;
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signal s_sqr_o: std_logic_vector(RD_WIDTH-1 downto 0);
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signal s_ine_o : std_logic;
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constant ITERATIONS : integer:= RD_WIDTH/2; -- iterations = N/2
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constant WIDTH_C : integer:= 5; -- log2(ITERATIONS)
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--0000000000000000000000000000000000000000000000000000
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constant CONST_B : std_logic_vector(RD_WIDTH-1 downto 0) :="0000000000000000000000000010000000000000000000000000"; -- b = 2^(N/2 - 1)
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constant CONST_B_2: std_logic_vector(RD_WIDTH-1 downto 0):="0100000000000000000000000000000000000000000000000000"; -- b^2
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constant CONST_C : std_logic_vector(WIDTH_C-1 downto 0):= "11010"; -- c = N/2
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signal s_count : integer range 0 to ITERATIONS;
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type t_state is (waiting,busy);
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signal s_state : t_state;
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signal b, b_2, r0, r0_2, r1, r1_2 : std_logic_vector(RD_WIDTH-1 downto 0);
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signal c : std_logic_vector(WIDTH_C-1 downto 0);
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signal s_op1, s_op2, s_sum1a, s_sum1b, s_sum2a, s_sum2b : std_logic_vector(RD_WIDTH-1 downto 0);
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begin
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-- Input Register
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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s_rad_i <= rad_i;
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s_start_i <= start_i;
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end if;
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end process;
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-- Output Register
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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sqr_o <= s_sqr_o(SQ_WIDTH-1 downto 0);
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ine_o <= s_ine_o;
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ready_o <= s_ready_o;
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end if;
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end process;
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-- FSM
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_start_i ='1' then
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s_state <= busy;
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s_count <= ITERATIONS;
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elsif s_count=0 and s_state=busy then
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s_state <= waiting;
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s_ready_o <= '1';
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s_count <=ITERATIONS;
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elsif s_state=busy then
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s_count <= s_count - 1;
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else
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s_state <= waiting;
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s_ready_o <= '0';
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end if;
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end if;
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end process;
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_start_i='1' then
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b <= CONST_B;
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b_2 <= CONST_B_2;
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c <= CONST_C;
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else
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b <= '0'&b(RD_WIDTH-1 downto 1); -- shr 1
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b_2 <= "00"&b_2(RD_WIDTH-1 downto 2);-- shr 2
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c <= c - '1';
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end if;
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end if;
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end process;
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s_op1 <= r0_2 + b_2;
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s_op2 <= shl(r0, c);
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s_sum1a <= "00000000000000000000000000"& (r0(25 downto 0) - b(25 downto 0));
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s_sum2a <= "00000000000000000000000000"& (r0(25 downto 0) + b(25 downto 0));
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s_sum1b <= s_op1 - s_op2;
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s_sum2b <= s_op1 + s_op2;
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process(clk_i)
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variable v_r1, v_r1_2 : std_logic_vector(RD_WIDTH-1 downto 0);
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begin
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if rising_edge(clk_i) then
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if s_start_i='1' then
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r0 <= (others =>'0');
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r0_2 <= (others =>'0');
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elsif s_state=busy then
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if r0_2 > s_rad_i then
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v_r1 := s_sum1a;
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v_r1_2 := s_sum1b;
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else
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v_r1 := s_sum2a;
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v_r1_2 := s_sum2b;
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end if;
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r0 <= v_r1;
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r0_2 <= v_r1_2;
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r1 <= v_r1;
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r1_2 <= v_r1_2;
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end if;
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end if;
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end process;
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_start_i = '1' then
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s_sqr_o <= (others =>'0');
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elsif s_count=0 then
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if r1_2 > s_rad_i then
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s_sqr_o <= r1 - '1';
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else
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s_sqr_o <= r1;
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end if;
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end if;
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end if;
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end process;
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-- check if result is inexact. In this way we saved 1 clk cycle!
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process(clk_i)
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variable v_r1_2 : std_logic_vector(RD_WIDTH-1 downto 0);
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begin
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if rising_edge(clk_i) then
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v_r1_2 := r1_2 - (r1(RD_WIDTH-2 downto 0)&"0") + '1';
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if s_count=0 then
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if r1_2 = s_rad_i or v_r1_2=s_rad_i then
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s_ine_o <= '0';
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else
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s_ine_o <= '1';
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end if;
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end if;
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end if;
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end process;
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end rtl;
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