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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [BCDAdd8NClk.sv] - Diff between revs 78 and 80

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Rev 78 Rev 80
Line 75... Line 75... 
reg [N*8-1:0] o2 [0:2];
 
reg [N*8-1:0] o2 [0:2];
 
wire [N-1:0] d [0:2];
 
wire [N-1:0] d [0:2];
 
 
 
 
 
genvar g,k;
 
genvar g,k;
 
generate begin : gBCDadd
 
generate begin : gBCDadd
 
for (g = 0; g < N; g = g + 1) begin
 
 
 
        for (k = 0; k < 3; k = k + 1) begin
 
        for (k = 0; k < 3; k = k + 1) begin
 
 
 
        for (g = 0; g < N; g = g + 1) begin
 
                initial begin
 
                initial begin
 
                        c[k][g] <= 'b0;
 
                        c[k][g] <= 'b0;
 
                end
 
                end
 
                BCDAdd u1 (
 
                BCDAdd u1 (
 
                        .ci(k==0 && g==0 ? ci : 1'b0),
 
                        .ci(k==0 && g==0 ? ci : 1'b0),

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