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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [fifos/] [fifo_mk2/] [1.0/] [vhd/] [ram_1clk.vhd] - Diff between revs 145 and 147

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Rev 145 Rev 147
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-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- File       : ram_1clk.vhd
 
-- File       : ram_1clk.vhd
 
-- Author     : Lasse Lehtonen
 
-- Author     : Lasse Lehtonen
 
-- Company    : 
-- Company    : 
-- Created    : 2011-01-13
 
-- Created    : 2011-01-13
 
-- Last update: 2011-10-19
 
-- Last update: 2012-06-14
 
-- Platform   : 
-- Platform   : 
-- Standard   : VHDL'93
 
-- Standard   : VHDL'93
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Description:
 
-- Description:
 
--
 
--
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architecture rtl of ram_1clk is
 
architecture rtl of ram_1clk is
 
 
 
 
 
  type ram_type is array (0 to depth_g-1)
 
  type ram_type is array (0 to depth_g-1)
 
    of std_logic_vector(data_width_g-1 downto 0);
 
    of std_logic_vector(data_width_g-1 downto 0);
 
 
 
 
 
  signal ram_r       : ram_type;
 
  signal ram_r       : ram_type := (others => (others => '0'));
 
  signal read_addr_r : integer range 0 to depth_g-1;
 
  signal read_addr_r : integer range 0 to depth_g-1;
 
 
 
 
 
begin  -- architecture rtl
 
begin  -- architecture rtl
 
 
 
 
 
  ram_p : process (clk) is
 
  ram_p : process (clk) is

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