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[/] [g729a_codec/] [trunk/] [VHDL/] [G729A_asip_addsub_pipeb.vhd] - Diff between revs 2 and 3

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Line 49... Line 49...
  );
  );
end G729A_ASIP_ADDSUB_PIPEB;
end G729A_ASIP_ADDSUB_PIPEB;
 
 
architecture ARC of G729A_ASIP_ADDSUB_PIPEB is
architecture ARC of G729A_ASIP_ADDSUB_PIPEB is
 
 
  constant ZERO : LDWORD_T := to_signed(0,LDLEN);
 
  constant ONE : LDWORD_T := to_signed(1,LDLEN);
 
 
 
  component G729A_ASIP_ADDER_F is
  component G729A_ASIP_ADDER_F is
    generic(
    generic(
      LEN1 : integer := 16;
      LEN1 : integer := 16;
      LEN2 : integer := 16
      LEN2 : integer := 16
    );
    );
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    XS(S'HIGH downto 0) := S;
    XS(S'HIGH downto 0) := S;
    XS(L-1 downto S'HIGH+1) := (others => S(S'HIGH));
    XS(L-1 downto S'HIGH+1) := (others => S(S'HIGH));
    return(XS);
    return(XS);
  end function;
  end function;
 
 
  signal IOPA,IOPB,CI,SUM : LDWORD_T;
  signal IOPA,IOPB,SUM : LDWORD_T;
 
  signal CI : std_logic;
 
 
begin
begin
 
 
  -- adder operands selection
  -- adder operands selection
  process(CTRL_i,OPB_i,OPA_i)
  process(CTRL_i,OPB_i,OPA_i)
  begin
  begin
    case CTRL_i is
    case CTRL_i is
      when AC_ABS|AC_NEG =>
      when AC_ABS|AC_NEG =>
        -- tmp = -opa_i
        -- tmp = -opa_i
        IOPA <= not(EXTS(OPA_i(SDLEN-1 downto 0),LDLEN));
        IOPA <= not(EXTS(OPA_i(SDLEN-1 downto 0),LDLEN));
        IOPB <= ZERO;
        IOPB <= (others => '0');
        CI <= ONE;
        CI <= '1';
      when AC_LABS|AC_LNEG =>
      when AC_LABS|AC_LNEG =>
        -- tmp = -opa_i
        -- tmp = -opa_i
        IOPA <= not(OPA_i);
        IOPA <= not(OPA_i);
        IOPB <= ZERO;
        IOPB <= (others => '0');
        CI <= ONE;
        CI <= '1';
      --when AC_ADD =>
      --when AC_ADD =>
      --  -- tmp = opa_i + opb_i
      --  -- tmp = opa_i + opb_i
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPB <= EXTS(OPB_i(SDLEN-1 downto 0),LDLEN);
      --  IOPB <= EXTS(OPB_i(SDLEN-1 downto 0),LDLEN);
      --  CI <= ZERO;
      --  CI <= '0';
      when AC_LADD =>
      when AC_LADD =>
        -- tmp = opa_i + opb_i
        -- tmp = opa_i + opb_i
        IOPA <= OPA_i;
        IOPA <= OPA_i;
        IOPB <= OPB_i;
        IOPB <= OPB_i;
        CI <= ZERO;
        CI <= '0';
      --when AC_SUB =>
      --when AC_SUB =>
      --  -- tmp = opa_i - opb_i
      --  -- tmp = opa_i - opb_i
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPB <= not(EXTS(OPB_i(SDLEN-1 downto 0),LDLEN));
      --  IOPB <= not(EXTS(OPB_i(SDLEN-1 downto 0),LDLEN));
      --  CI <= ONE;
      --  CI <= '1';
      when AC_LSUB =>
      when AC_LSUB =>
        -- tmp = opa_i - opb_i
        -- tmp = opa_i - opb_i
        IOPA <= OPA_i;
        IOPA <= OPA_i;
        IOPB <= not(OPB_i);
        IOPB <= not(OPB_i);
        CI <= ONE;
        CI <= '1';
      when AC_LEXT =>
      when AC_LEXT =>
        -- tmp = opa_i - (opa_i(31:16)<<16)
        -- tmp = opa_i - (opa_i(31:16)<<16)
        IOPA <= OPA_i;
        IOPA <= OPA_i;
        IOPB <= not(OPA_i(LDLEN-1 downto SDLEN) & to_signed(0,SDLEN));
        IOPB <= not(OPA_i(LDLEN-1 downto SDLEN) & to_signed(0,SDLEN));
        CI <= ONE;
        CI <= '1';
      when others => -- RND
      when others => -- RND
        -- tmp = opa_i + 0x00008000 
        -- tmp = opa_i + 0x00008000 
        IOPA <= OPA_i;
        IOPA <= OPA_i;
        IOPB <= (SDLEN-1 => '1',others => '0');
        IOPB <= (SDLEN-1 => '1',others => '0');
        CI <= ZERO;
        CI <= '0';
      --when AC_INC =>
      --when AC_INC =>
      --  -- tmp = opa_i + 1 
      --  -- tmp = opa_i + 1 
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPB <= (0 => '1',others => '0');
      --  IOPB <= (0 => '1',others => '0');
      --  CI <= ZERO;
      --  CI <= '0';
      --when others => -- DEC
      --when others => -- DEC
      --  -- tmp = opa_i - 1 
      --  -- tmp = opa_i - 1 
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
      --  IOPB <= (others => '1');
      --  IOPB <= (others => '1');
      --  CI <= ZERO;
      --  CI <= '0';
    end case;
    end case;
  end process;
  end process;
 
 
  -- adder
  -- adder
 
 
Line 145... Line 143...
      LEN2 => SDLEN
      LEN2 => SDLEN
    )
    )
    port map(
    port map(
      OPA_i => IOPA,
      OPA_i => IOPA,
      OPB_i => IOPB,
      OPB_i => IOPB,
      CI_i => CI(0),
      CI_i => CI,
      SUM_o => SUM
      SUM_o => SUM
    );
    );
 
 
  -- result and overflow flag generation
  -- result and overflow flag generation
  process(CTRL_i,OPA_i,OPB_i,SUM)
  process(CTRL_i,OPA_i,OPB_i,SUM)

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