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Line 75... |
* desired file for your board
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* desired file for your board
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*/
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*/
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extern const char InitData[7];
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extern const char InitData[7];
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/** private flag to signal, that the GPIF receives data from the FPGA */
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//** private flag to signal, that the GPIF receives data from the FPGA */
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volatile static uint8_t flGPIF;
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//volatile static uint8_t flGPIF;
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/**
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/**
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* \brief exectuted when the gpif wafeform terminates
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* \brief exectuted when the gpif wafeform terminates
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Line 88... |
void
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void
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isr_gpif_done (void) interrupt
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isr_gpif_done (void) interrupt
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{
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{
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ISR_DEBUG_PORT |= bmGPIF_DONE;
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ISR_DEBUG_PORT |= bmGPIF_DONE;
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clear_fifo_gpif_irq();
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//EA = 0; /* disable all interrupts */
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/* check if there is data available for an OUT transfer */
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/* check if there is data available for an OUT transfer */
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if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
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/*if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
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//if(!(EP2468STAT & bmEP2EMPTY)) {
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//if(!(EP2468STAT & bmEP2EMPTY)) {
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flGPIF &= ~bmGPIF_PENDING_DATA;
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flGPIF &= ~bmGPIF_PENDING_DATA;
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GPIFABORT = 0xFF;
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GPIFABORT = 0xFF;
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SYNCDELAY;
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SYNCDELAY;
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gpif_trigger_write();
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gpif_trigger_write();
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}
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}
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else {
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else*/ {
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INPKTEND = USB_TMC_EP_IN;
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/* check if this is a end of a IN transfer */
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//INPKTEND = USB_TMC_EP_IN;
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while(!(GPIFTRIG & bmGPIF_IDLE));
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gpif_trigger_read();
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gpif_trigger_read();
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}
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}
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//EA = 1; /* global interrupt enable */
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clear_fifo_gpif_irq();
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ISR_DEBUG_PORT &= ~bmGPIF_DONE;
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ISR_DEBUG_PORT &= ~bmGPIF_DONE;
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}
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}
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Line 117... |
void
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void
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isr_endpoint_out_data (void) interrupt
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isr_endpoint_out_data (void) interrupt
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{
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{
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ISR_DEBUG_PORT |= bmFIFO_PF;
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ISR_DEBUG_PORT |= bmFIFO_PF;
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clear_fifo_gpif_irq();
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/* check if there is a active IN transfer */
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/* check if there is a active IN transfer */
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if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
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/*if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
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flGPIF |= bmGPIF_PENDING_DATA;
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flGPIF |= bmGPIF_PENDING_DATA;
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}
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}
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else {
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else*/ {
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//EA = 0; /* disable all interrupts */
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GPIFABORT = 0xFF;
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GPIFABORT = 0xFF;
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SYNCDELAY;
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SYNCDELAY;
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while(!(GPIFTRIG & bmGPIF_IDLE));
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gpif_trigger_write();
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gpif_trigger_write();
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//EA = 1; /* global interrupt enable */
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}
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}
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clear_fifo_gpif_irq();
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ISR_DEBUG_PORT &= ~bmFIFO_PF;
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ISR_DEBUG_PORT &= ~bmFIFO_PF;
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}
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}
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/** \brief initialize GPIF system */
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/** \brief initialize GPIF system */
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void init_gpif (void)
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void init_gpif (void)
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{
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{
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uint8_t i;
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uint8_t i;
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#ifdef GECKO3MAIN
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#ifdef GECKO3MAIN
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/* IFCLK is generated internally and runs at 48 MHz; GPIF "master mode" */
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/* IFCLK is generated internally and runs at 30 MHz; GPIF "master mode" */
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IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmGSTATE | bmIFGPIF;
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//IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmGSTATE | bmIFGPIF;
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IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmGSTATE | bmIFGPIF;
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SYNCDELAY;
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SYNCDELAY;
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/* we have to commit the currently processed packet BEFORE we switch to auto out mode */
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/* we have to commit the currently processed packet BEFORE we switch to auto out mode */
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OUTPKTEND = bmSKIP | USB_TMC_EP_OUT;
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OUTPKTEND = bmSKIP | USB_TMC_EP_OUT;
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Line 164... |
* we use the programmable flag as interrupt source to detect if data for the
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* we use the programmable flag as interrupt source to detect if data for the
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* FPGA is available and as GPIF flag to stop the flowstate, for this the
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* FPGA is available and as GPIF flag to stop the flowstate, for this the
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* flag has to change one cycle before the FIFO is completly empty, else we
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* flag has to change one cycle before the FIFO is completly empty, else we
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* transfer one word too much */
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* transfer one word too much */
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EP2FIFOPFH = bmDECIS;
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EP2FIFOPFH = bmDECIS;
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EP2FIFOPFL = 1;
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EP2FIFOPFL = 4;
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SYNCDELAY;
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SYNCDELAY;
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//EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE;
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EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE;
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EP2GPIFFLGSEL = bmFLAG_EMPTY;
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//EP2GPIFFLGSEL = bmFLAG_EMPTY;
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SYNCDELAY;
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SYNCDELAY;
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EP6GPIFFLGSEL = bmFLAG_FULL;
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EP6GPIFFLGSEL = bmFLAG_FULL;
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SYNCDELAY;
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SYNCDELAY;
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EP2GPIFPFSTOP = 0;
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EP2GPIFPFSTOP = 0;
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Line 282... |
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flGPIF = 0; /* unset all internal GPIF flags */
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flGPIF = 0; /* unset all internal GPIF flags */
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#ifdef GECKO3MAIN
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#ifdef GECKO3MAIN
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//EP2FIFOCFG &= ~bmOEP;
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EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */
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EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */
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SYNCDELAY;
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SYNCDELAY;
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//EP6FIFOCFG &= ~bmINFM;
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//EP6FIFOCFG &= ~bmINFM;
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EP6FIFOCFG &= ~bmAUTOIN; /* disable AutoIN feature */
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EP6FIFOCFG &= ~bmAUTOIN; /* disable AutoIN feature */
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