| Line 31... |
Line 31... |
-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
|
-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
|
--
|
--
|
-- This core provides a simple FIFO and register interface to the
|
-- This core provides a simple FIFO and register interface to the
|
-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
|
-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
|
--
|
--
|
-- Look at GECKO3COM_loopback.vhd for an example how to use it.
|
-- Look at GECKO3COM_simple.vhd for an example how to use it.
|
--
|
--
|
-- Target Devices: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
|
-- Target Devices: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
|
-- Tool versions: 11.1
|
-- Tool versions: 11.1
|
--
|
--
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
| Line 66... |
Line 66... |
i_send_fifo_wr_en : in std_logic;
|
i_send_fifo_wr_en : in std_logic;
|
o_send_fifo_full : out std_logic;
|
o_send_fifo_full : out std_logic;
|
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
|
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
|
i_send_transfersize : in std_logic_vector(31 downto 0);
|
i_send_transfersize : in std_logic_vector(31 downto 0);
|
i_send_transfersize_en : in std_logic;
|
i_send_transfersize_en : in std_logic;
|
|
i_send_have_more_data : in std_logic;
|
o_send_data_request : out std_logic;
|
o_send_data_request : out std_logic;
|
o_send_finished : out std_logic;
|
o_send_finished : out std_logic;
|
|
|
o_rx : out std_logic; -- receiving data signalisation
|
o_rx : out std_logic; -- receiving data signalisation
|
o_tx : out std_logic; -- transmitting data signalisation
|
o_tx : out std_logic; -- transmitting data signalisation
|
| Line 144... |
Line 145... |
o_send_fifo_full : out std_logic;
|
o_send_fifo_full : out std_logic;
|
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
|
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
|
i_send_fifo_reset : in std_logic;
|
i_send_fifo_reset : in std_logic;
|
i_send_transfersize : in std_logic_vector(31 downto 0);
|
i_send_transfersize : in std_logic_vector(31 downto 0);
|
i_send_transfersize_en : in std_logic;
|
i_send_transfersize_en : in std_logic;
|
|
i_send_have_more_data : in std_logic;
|
i_send_counter_load : in std_logic;
|
i_send_counter_load : in std_logic;
|
i_send_counter_en : in std_logic;
|
i_send_counter_en : in std_logic;
|
o_send_counter_zero : out std_logic;
|
o_send_counter_zero : out std_logic;
|
i_send_mux_sel : in std_logic_vector(2 downto 0);
|
i_send_mux_sel : in std_logic_vector(2 downto 0);
|
o_send_finished : out std_logic;
|
o_send_finished : out std_logic;
|
| Line 299... |
Line 301... |
o_send_fifo_full => o_send_fifo_full,
|
o_send_fifo_full => o_send_fifo_full,
|
i_send_fifo_data => i_send_fifo_data,
|
i_send_fifo_data => i_send_fifo_data,
|
i_send_fifo_reset => s_send_fifo_reset,
|
i_send_fifo_reset => s_send_fifo_reset,
|
i_send_transfersize => i_send_transfersize,
|
i_send_transfersize => i_send_transfersize,
|
i_send_transfersize_en => i_send_transfersize_en,
|
i_send_transfersize_en => i_send_transfersize_en,
|
|
i_send_have_more_data => i_send_have_more_data,
|
i_send_counter_load => s_send_counter_load,
|
i_send_counter_load => s_send_counter_load,
|
i_send_counter_en => s_send_counter_en,
|
i_send_counter_en => s_send_counter_en,
|
o_send_counter_zero => s_send_counter_zero,
|
o_send_counter_zero => s_send_counter_zero,
|
i_send_mux_sel => s_send_mux_sel,
|
i_send_mux_sel => s_send_mux_sel,
|
i_receive_newdata_set => s_receive_newdata_set,
|
i_receive_newdata_set => s_receive_newdata_set,
|
