| Line 31... |
Line 31... |
-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
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-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
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--
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--
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-- This core provides a simple FIFO and register interface to the
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-- This core provides a simple FIFO and register interface to the
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
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--
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--
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-- Look at GECKO3COM_loopback.vhd for an example how to use it.
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-- Look at GECKO3COM_simple_test.vhd for an example how to use it.
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--
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--
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-- Target Devices: general
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-- Target Devices: general
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-- Tool versions: 11.1
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-- Tool versions: 11.1
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-- Dependencies: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
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-- Dependencies: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
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--
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--
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| Line 85... |
Line 85... |
o_send_fifo_full : out std_logic;
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o_send_fifo_full : out std_logic;
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
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i_send_fifo_reset : in std_logic;
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i_send_fifo_reset : in std_logic;
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize : in std_logic_vector(31 downto 0);
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i_send_transfersize_en : in std_logic;
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i_send_transfersize_en : in std_logic;
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i_send_have_more_data : in std_logic;
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i_send_counter_load : in std_logic;
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i_send_counter_load : in std_logic;
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i_send_counter_en : in std_logic;
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i_send_counter_en : in std_logic;
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o_send_counter_zero : out std_logic;
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o_send_counter_zero : out std_logic;
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i_send_mux_sel : in std_logic_vector(2 downto 0);
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i_send_mux_sel : in std_logic_vector(2 downto 0);
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| Line 147... |
Line 148... |
signal s_send_transfersize_count: std_logic_vector(31 downto 0);
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signal s_send_transfersize_count: std_logic_vector(31 downto 0);
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signal s_receive_fifo_empty : std_logic;
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signal s_receive_fifo_empty : std_logic;
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signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_btag, s_nbtag : std_logic_vector(7 downto 0);
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signal s_btag, s_nbtag, s_msg_id: std_logic_vector(7 downto 0);
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begin -- behaviour
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begin -- behaviour
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receive_fifo_1 : receive_fifo
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receive_fifo_1 : receive_fifo
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generic map (
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generic map (
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| Line 246... |
Line 247... |
-- type : sequential
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
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-- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
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-- i_send_transfersize_en
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-- i_send_transfersize_en
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-- outputs: s_send_transfersize_count
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-- outputs: s_send_transfersize_count
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send_counter : process (i_sysclk, i_nReset)
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send_counter : process (i_sysclk, i_nReset)
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begin -- process receive_counter
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begin -- process send_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_send_transfersize_count <= (others => '0');
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s_send_transfersize_count <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_send_counter_load = '1' then
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if i_send_counter_load = '1' then
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s_receive_transfersize_count <= s_send_transfersize_reg;
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s_send_transfersize_count <= s_send_transfersize_reg;
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end if;
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end if;
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if i_send_counter_en = '1' then
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if i_send_counter_en = '1' then
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s_send_transfersize_count <= s_send_transfersize_count - 1;
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s_send_transfersize_count <= s_send_transfersize_count - 1;
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end if;
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end if;
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end if;
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end if;
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| Line 270... |
Line 271... |
-- type : sequential
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
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-- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
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-- i_rx_data
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-- i_rx_data
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-- outputs: s_btag, s_nbtag
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-- outputs: s_btag, s_nbtag
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btag_register : process (i_sysclk, i_nReset)
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btag_register : process (i_sysclk, i_nReset)
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begin -- process receive_counter
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begin -- process btag_register
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if i_nReset = '0' then -- asynchronous reset (active low)
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_btag <= (others => '0');
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s_btag <= (others => '0');
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s_msg_id <= (others => '0');
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s_nbtag <= (others => '0');
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s_nbtag <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_btag_reg_en = '1' then
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if i_btag_reg_en = '1' then
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s_btag <= i_rx_data(15 downto 8);
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s_btag <= i_rx_data(15 downto 8);
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s_msg_id <= i_rx_data(7 downto 0);
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end if;
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end if;
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if i_nbtag_reg_en = '1' then
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if i_nbtag_reg_en = '1' then
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s_nbtag <= i_rx_data(7 downto 0);
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s_nbtag <= i_rx_data(7 downto 0);
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end if;
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end if;
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end if;
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end if;
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| Line 290... |
Line 293... |
'1' when s_btag = not s_nbtag else
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'1' when s_btag = not s_nbtag else
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'0';
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'0';
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o_dev_dep_msg_out <=
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o_dev_dep_msg_out <=
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'1' when i_rx_data(7 downto 0) = x"01" else
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'1' when s_msg_id(7 downto 0) = x"01" else
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'0';
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'0';
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o_request_dev_dep_msg_in <=
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o_request_dev_dep_msg_in <=
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'1' when i_rx_data(7 downto 0) = x"02" else
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'1' when s_msg_id(7 downto 0) = x"02" else
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'0';
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'0';
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o_eom_bit_detected <=
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o_eom_bit_detected <=
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'1' when i_rx_data(15 downto 8) = b"00000001" else
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'1' when i_rx_data(15 downto 8) = b"00000001" else
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'0';
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'0';
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| Line 315... |
Line 318... |
case i_send_mux_sel is
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case i_send_mux_sel is
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when "000" => o_tx_data <= x"02" & s_btag; -- MsgID and stored bTag
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when "000" => o_tx_data <= x"02" & s_btag; -- MsgID and stored bTag
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when "001" => o_tx_data <= s_nbtag & x"00"; -- inverted bTag and Reserved
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when "001" => o_tx_data <= s_nbtag & x"00"; -- inverted bTag and Reserved
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when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
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when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
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when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
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when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
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when "100" => o_tx_data <= x"0001"; -- TransferAttributes: EOM = 1
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--TransferAttributes EOM bit:
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when "100" => o_tx_data <= b"000000000000000" & i_send_have_more_data;
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when "101" => o_tx_data <= x"0000"; -- Header byte 10 and 11, Reserved
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when "101" => o_tx_data <= x"0000"; -- Header byte 10 and 11, Reserved
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when "110" => o_tx_data <= s_send_fifo_data; -- message data
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when "110" => o_tx_data <= s_send_fifo_data; -- message data
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when others => o_tx_data <= s_send_fifo_data;
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when others => o_tx_data <= s_send_fifo_data;
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end case;
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end case;
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end process tx_data_mux;
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end process tx_data_mux;
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| Line 330... |
Line 334... |
-- inputs : i_sysclk, i_nReset, i_receive_newdata_set,
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-- inputs : i_sysclk, i_nReset, i_receive_newdata_set,
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-- i_receive_end_of_message_set, s_send_data_request_set,
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-- i_receive_end_of_message_set, s_send_data_request_set,
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-- i_receive_fifo_rd_en, s_receive_fifo_empty, i_send_fifo_wr_en
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-- i_receive_fifo_rd_en, s_receive_fifo_empty, i_send_fifo_wr_en
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-- outputs: o_receive_newdata, o_receive_end_of_message, o_send_data_request
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-- outputs: o_receive_newdata, o_receive_end_of_message, o_send_data_request
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gecko3com_simple_flags: process (i_sysclk, i_nReset)
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gecko3com_simple_flags: process (i_sysclk, i_nReset)
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variable v_receive_fifo_empty_old : std_logic;
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begin -- process gecko3com_simple_flags
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begin -- process gecko3com_simple_flags
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if i_nReset = '0' then -- asynchronous reset (active low)
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if i_nReset = '0' then -- asynchronous reset (active low)
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o_receive_newdata <= '0';
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o_receive_newdata <= '0';
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o_receive_end_of_message <= '0';
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o_receive_end_of_message <= '0';
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o_send_data_request <= '0';
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o_send_data_request <= '0';
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v_receive_fifo_empty_old := '0';
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_receive_newdata_set = '1' then
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if i_receive_newdata_set = '1' then
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o_receive_newdata <= '1';
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o_receive_newdata <= '1';
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end if;
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end if;
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if i_receive_fifo_rd_en = '1' then
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if i_receive_fifo_rd_en = '1' then
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| Line 346... |
Line 352... |
end if;
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end if;
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if i_receive_end_of_message_set = '1' then
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if i_receive_end_of_message_set = '1' then
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o_receive_end_of_message <= '1';
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o_receive_end_of_message <= '1';
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end if;
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end if;
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if s_receive_fifo_empty = '1' then
|
if s_receive_fifo_empty = '1' and v_receive_fifo_empty_old = '0' then
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o_receive_end_of_message <= '0';
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o_receive_end_of_message <= '0';
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end if;
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end if;
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v_receive_fifo_empty_old := s_receive_fifo_empty;
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|
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if i_send_data_request_set = '1' then
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if i_send_data_request_set = '1' then
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o_send_data_request <= '1';
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o_send_data_request <= '1';
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end if;
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end if;
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if i_send_fifo_wr_en = '1' then
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if i_send_fifo_wr_en = '1' then
|
