| Line 67... |
Line 67... |
o_receive_fifo_full : out std_logic;
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o_receive_fifo_full : out std_logic;
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
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i_receive_fifo_reset : in std_logic;
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i_receive_fifo_reset : in std_logic;
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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o_receive_transfersize : out std_logic_vector(31 downto 0);
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i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
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o_receive_transfersize_lsb : out std_logic;
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i_receive_counter_load : in std_logic;
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i_receive_counter_load : in std_logic;
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i_receive_counter_en : in std_logic;
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i_receive_counter_en : in std_logic;
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o_receive_counter_zero : out std_logic;
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o_receive_counter_zero : out std_logic;
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o_dev_dep_msg_out : out std_logic;
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o_dev_dep_msg_out : out std_logic;
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o_request_dev_dep_msg_in : out std_logic;
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o_request_dev_dep_msg_in : out std_logic;
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| Line 142... |
Line 143... |
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal s_receive_transfersize : std_logic_vector(31 downto 0);
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signal s_receive_transfersize : std_logic_vector(31 downto 0);
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signal s_send_transfersize_reg: std_logic_vector(31 downto 0);
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signal s_send_transfersize_reg: std_logic_vector(31 downto 0);
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signal s_receive_transfersize_count: std_logic_vector(31 downto 0);
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signal s_receive_transfersize_count : std_logic_vector(30 downto 0);
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signal s_send_transfersize_count: std_logic_vector(31 downto 0);
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signal s_send_transfersize_count : std_logic_vector(30 downto 0);
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signal s_receive_fifo_empty : std_logic;
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signal s_receive_fifo_empty : std_logic;
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signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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signal s_btag, s_nbtag, s_msg_id: std_logic_vector(7 downto 0);
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signal s_btag, s_nbtag, s_msg_id: std_logic_vector(7 downto 0);
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Line 201... |
end if;
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end if;
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end if;
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end if;
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end process receive_transfersize;
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end process receive_transfersize;
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o_receive_transfersize <= s_receive_transfersize;
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o_receive_transfersize <= s_receive_transfersize;
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o_receive_transfersize_lsb <= s_receive_transfersize(0);
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-- purpose: 32 bit send_transfersize register
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-- purpose: 32 bit send_transfersize register
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-- type : sequential
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, i_send_transfersize, i_receive_transfersize_en
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-- inputs : i_sysclk, i_nReset, i_send_transfersize, i_receive_transfersize_en
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| Line 228... |
Line 230... |
begin -- process receive_counter
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begin -- process receive_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_receive_transfersize_count <= (others => '0');
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s_receive_transfersize_count <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_receive_counter_load = '1' then
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if i_receive_counter_load = '1' then
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s_receive_transfersize_count <= s_receive_transfersize;
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s_receive_transfersize_count <= s_receive_transfersize(31 downto 1);
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end if;
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elsif i_receive_counter_en = '1' then
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if i_receive_counter_en = '1' then
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s_receive_transfersize_count <= s_receive_transfersize_count - 1;
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s_receive_transfersize_count <= s_receive_transfersize_count - 1;
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else
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s_receive_transfersize_count <= s_receive_transfersize_count;
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end if;
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end if;
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end if;
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end if;
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end process receive_counter;
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end process receive_counter;
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o_receive_counter_zero <=
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o_receive_counter_zero <=
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'1' when s_receive_transfersize_count = x"0000" else
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'1' when s_receive_transfersize_count = "000000000000000000000000000000"
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'0';
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else '0';
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-- purpose: down counter for the send transfer size
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-- purpose: down counter for the send transfer size
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-- type : sequential
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
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-- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
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| Line 252... |
Line 255... |
begin -- process send_counter
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begin -- process send_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
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if i_nReset = '0' then -- asynchronous reset (active low)
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s_send_transfersize_count <= (others => '0');
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s_send_transfersize_count <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
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if i_send_counter_load = '1' then
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if i_send_counter_load = '1' then
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s_send_transfersize_count <= s_send_transfersize_reg;
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s_send_transfersize_count <= s_send_transfersize_reg(31 downto 1);
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end if;
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elsif i_send_counter_en = '1' then
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if i_send_counter_en = '1' then
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s_send_transfersize_count <= s_send_transfersize_count - 1;
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s_send_transfersize_count <= s_send_transfersize_count - 1;
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else
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s_send_transfersize_count <= s_send_transfersize_count;
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end if;
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end if;
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end if;
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end if;
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end process send_counter;
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end process send_counter;
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o_send_counter_zero <=
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o_send_counter_zero <=
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'1' when s_send_transfersize_count = x"0000" else
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'1' when s_send_transfersize_count = "000000000000000000000000000000"
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'0';
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else '0';
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-- purpose: registers to store the btag and inverse btag
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-- purpose: registers to store the btag and inverse btag
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-- type : sequential
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-- type : sequential
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-- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
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-- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
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| Line 301... |
Line 305... |
o_request_dev_dep_msg_in <=
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o_request_dev_dep_msg_in <=
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'1' when s_msg_id(7 downto 0) = x"02" else
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'1' when s_msg_id(7 downto 0) = x"02" else
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'0';
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'0';
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o_eom_bit_detected <=
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o_eom_bit_detected <=
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'1' when i_rx_data(15 downto 8) = b"00000001" else
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'1' when i_rx_data(7 downto 0) = b"00000001" else
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'0';
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'0';
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-- purpose: mulitiplexer to construct the tmc header structure
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-- purpose: mulitiplexer to construct the tmc header structure
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-- type : combinational
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-- type : combinational
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| Line 314... |
Line 318... |
-- outputs: o_tx_data
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-- outputs: o_tx_data
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tx_data_mux: process (i_send_mux_sel, i_send_have_more_data, s_btag,
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tx_data_mux: process (i_send_mux_sel, i_send_have_more_data, s_btag,
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s_nbtag, s_send_fifo_data, s_send_transfersize_reg)
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s_nbtag, s_send_fifo_data, s_send_transfersize_reg)
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begin -- process tx_data_mux
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begin -- process tx_data_mux
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case i_send_mux_sel is
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case i_send_mux_sel is
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when "000" => o_tx_data <= x"02" & s_btag; -- MsgID and stored bTag
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when "000" => o_tx_data <= s_btag & s_msg_id; -- MsgID and stored bTag
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when "001" => o_tx_data <= s_nbtag & x"00"; -- inverted bTag and Reserved
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when "001" => o_tx_data <= x"00" & s_nbtag; -- inverted bTag and Reserved
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when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
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when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
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when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
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when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
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--TransferAttributes EOM bit:
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--TransferAttributes EOM bit:
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when "100" => o_tx_data <= b"000000000000000" & i_send_have_more_data;
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when "100" => o_tx_data <= b"000000000000000" & not i_send_have_more_data;
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when "101" => o_tx_data <= x"0000"; -- Header byte 10 and 11, Reserved
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when "101" => o_tx_data <= x"0000"; -- Header byte 10 and 11, Reserved
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when "110" => o_tx_data <= s_send_fifo_data; -- message data
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when "110" => o_tx_data <= s_send_fifo_data; -- message data
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when others => o_tx_data <= s_send_fifo_data;
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when others => o_tx_data <= s_btag & s_msg_id; -- MsgID and stored bTag
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end case;
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end case;
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end process tx_data_mux;
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end process tx_data_mux;
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-- purpose: set and reset behavour for the status flags
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-- purpose: set and reset behavour for the status flags
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