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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [gpif_com.vhd] - Diff between revs 28 and 29

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Rev 28 Rev 29
Line 76... Line 76...
 
 
 
 
architecture structure of gpif_com is
architecture structure of gpif_com is
 
 
  -- interconection signals
  -- interconection signals
 
 
  signal s_FIFOrst, s_WRX, s_RDYX      : std_logic;
  signal s_FIFOrst, s_WRX, s_RDYX      : std_logic;
 
 
  signal s_ABORT_FSM, s_ABORT_TMP  : std_logic;
  signal s_ABORT_FSM, s_ABORT_TMP  : std_logic;
  signal s_RX_FSM, s_RX_TMP  : std_logic;
  signal s_RX_FSM, s_RX_TMP  : std_logic;
  signal s_TX_FSM, s_TX_TMP  : std_logic;
  signal s_TX_FSM, s_TX_TMP  : std_logic;
Line 111... Line 110...
 
 
  -- data signals
  -- data signals
  signal s_dbus_trans_dir     : std_logic;
  signal s_dbus_trans_dir     : std_logic;
  signal s_dbus_in  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
  signal s_dbus_in  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
  signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
  signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
  signal s_dbus_out_fifo  : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- COMPONENTS
  -- COMPONENTS
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
Line 189... Line 189...
      i_rst          => s_FIFOrst,
      i_rst          => s_FIFOrst,
      i_wr_clk       => i_SYSCLK,
      i_wr_clk       => i_SYSCLK,
      i_wr_en        => s_X2U_WR_EN,
      i_wr_en        => s_X2U_WR_EN,
      o_almost_empty => s_X2U_AM_EMPTY,
      o_almost_empty => s_X2U_AM_EMPTY,
      o_almost_full  => s_X2U_AM_FULL,
      o_almost_full  => s_X2U_AM_FULL,
      o_dout         => s_dbus_out,
      o_dout         => s_dbus_out_fifo,
      o_empty        => s_X2U_EMPTY,
      o_empty        => s_X2U_EMPTY,
      o_full         => s_X2U_FULL
      o_full         => s_X2U_FULL
      );
      );
 
 
 
 
Line 307... Line 307...
  -- usb to xilinx transfer is read twice.
  -- usb to xilinx transfer is read twice.
  buf_input : process (i_IFCLK)
  buf_input : process (i_IFCLK)
  begin
  begin
    if rising_edge(i_IFCLK) then
    if rising_edge(i_IFCLK) then
      s_dbus_in <= b_gpif_bus;
      s_dbus_in <= b_gpif_bus;
 
 
 
      if s_X2U_RD_EN = '1' then
 
        s_dbus_out <= s_dbus_out_fifo;
 
      end if;
    end if;
    end if;
  end process buf_input;
  end process buf_input;
 
 
 
 
end structure;
end structure;

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