| Line 92... |
Line 92... |
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type t_fsmState is (rst, idle, -- controll states
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type t_fsmState is (rst, idle, -- controll states
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inRQ, inACK, inWait, inTrans, inThrot,
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inRQ, inACK, inWait, inTrans, inThrot,
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inThrotBreak,inThrotBreak2, inThrotEnd,
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inThrotBreak,inThrotBreak2, inThrotEnd,
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endInTrans, -- in com states
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endInTrans, -- in com states
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outRQ, outTrans, outACK, outUSBwait, outFIFOwait,
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outRQ, outRQdelay, outTrans, outACK, outUSBwait,
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endOutTrans); -- out com states
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outFIFOwait, endOutTrans); -- out com states
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signal pr_state, nx_state : t_fsmState;
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signal pr_state, nx_state : t_fsmState;
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-- XST specific synthesize attributes
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-- XST specific synthesize attributes
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attribute safe_recovery_state of pr_state : signal is "idle";
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attribute safe_recovery_state of pr_state : signal is "idle";
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attribute safe_implementation of pr_state : signal is "yes";
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attribute safe_implementation of pr_state : signal is "yes";
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-- interconection signals
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-- interconection signals
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signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
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signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
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-- USB to Xilinx (U2X)
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-- USB to Xilinx (U2X)
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signal s_U2X_WR_EN : std_logic;
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signal s_U2X_WR_EN : std_logic;
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Line 357... |
if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_WRU = '1' and i_RDYU = '0' then
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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nx_state <= inRQ;
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else
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else
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nx_state <= outRQdelay;
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end if;
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when outRQdelay =>
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-- output signal values:
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s_WRX <= '1';
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s_RDYX <= '0';
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s_X2U_RD_EN <= '0';
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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elsif i_WRU = '1' and i_RDYU = '0' then
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nx_state <= inRQ;
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else
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nx_state <= outACK;
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nx_state <= outACK;
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end if;
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end if;
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when outACK =>
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when outACK =>
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state_number := x"C";
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state_number := x"C";
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| Line 413... |
Line 426... |
s_bus_trans_dir <= writeToGPIF;
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s_bus_trans_dir <= writeToGPIF;
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-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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nx_state <= endOutTrans;
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elsif i_WRU = '0' and i_RDYU = '1' then
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elsif i_WRU = '0' and i_RDYU = '1' then
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nx_state <= outTrans;
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nx_state <= outTrans;
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else
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else
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nx_state <= outUSBwait;
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nx_state <= outUSBwait;
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end if;
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end if;
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| Line 433... |
Line 448... |
-- state decisions
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-- state decisions
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if i_WRU = '1' and i_RDYU = '1' then
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if i_WRU = '1' and i_RDYU = '1' then
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nx_state <= rst;
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nx_state <= rst;
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
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nx_state <= endOutTrans;
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nx_state <= endOutTrans;
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elsif i_X2U_EMPTY = '0' and i_EOM = '0' then
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elsif i_X2U_EMPTY = '0' then
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nx_state <= outTrans;
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nx_state <= outTrans;
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else
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else
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nx_state <= outFIFOwait;
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nx_state <= outFIFOwait;
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end if;
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end if;
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