URL https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk

Subversion Repositories gpib_controller

[/] [gpib_controller/] [trunk/] [prototype_1/] [fpga/] [xilinx_prj/] [main_bitgen.xwbt] - Diff between revs 5 and 8

Rev 5	Rev 8
Line 1...	Line 1...
`INTSTYLE=ise`	`INTSTYLE=ise`
`INFILE=/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/main.ncd`	`INFILE=/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/main.ncd`
`OUTFILE=/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/main.bit`	`OUTFILE=/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/main.bit`
`FAMILY=Spartan3`	`FAMILY=Spartan3`
`PART=xc3s200-4tq144`	`PART=xc3s200-4tq144`
`WORKINGDIR=/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1`	`WORKINGDIR=/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj`
`LICENSE=WebPack`	`LICENSE=WebPack`
`USER_INFO=0_0_730`	`USER_INFO=0_0_730`