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# |
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# |
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# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0
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# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0
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# | BABY&HW 2012.03.31.21:26:56
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# | BABY&HW 2012.03.31.21:26:56
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# | Hardware Assisted IEEE 1588 IP Core
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# | Hardware Assisted IEEE 1588 IP Core
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# |
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# |
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# | ha1588.v
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# | ha1588_avl.v
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# |
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# |
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# | ../../../par/altera/ip/define.h syn, sim
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# | ../../../par/altera/ip/dcfifo_128b_16.v syn, sim
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# | ../../../rtl/top/ha1588.v syn, sim
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# | ../../../rtl/top/ha1588.v syn, sim
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# | ../../../rtl/reg/reg.v syn, sim
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# | ../../../rtl/reg/reg.v syn, sim
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# | ../../../rtl/rtc/rtc.v syn, sim
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# | ../../../rtl/rtc/rtc.v syn, sim
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# | ../../../rtl/tsu/tsu.v syn, sim
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# | ../../../rtl/tsu/tsu.v syn, sim
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# | ../../../rtl/tsu/ptp_parser.v syn, sim
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# | ../../../rtl/tsu/ptp_parser.v syn, sim
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package require -exact sopc 10.1
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package require -exact sopc 10.1
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# |
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# |
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# +-----------------------------------
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# +-----------------------------------
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# +-----------------------------------
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# +-----------------------------------
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# | module ha1588
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# | module ha1588_avl
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# |
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# |
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set_module_property DESCRIPTION "Hardware Assisted IEEE 1588 IP Core"
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set_module_property DESCRIPTION "Hardware Assisted IEEE 1588 IP Core"
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set_module_property NAME ha1588
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set_module_property NAME ha1588_avl
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set_module_property VERSION 1.0
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR "BABY&HW"
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set_module_property AUTHOR "BABY&HW"
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set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core"
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set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core"
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set_module_property TOP_LEVEL_HDL_FILE ha1588.v
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set_module_property TOP_LEVEL_HDL_FILE ha1588_avl.v
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set_module_property TOP_LEVEL_HDL_MODULE ha1588
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set_module_property TOP_LEVEL_HDL_MODULE ha1588_avl
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL TRUE
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set_module_property ANALYZE_HDL TRUE
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# |
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# |
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# +-----------------------------------
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# +-----------------------------------
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# +-----------------------------------
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# +-----------------------------------
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# | files
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# | files
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# |
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# |
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add_file ha1588_avl.v {SYNTHESIS SIMULATION}
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add_file ../../../par/altera/ip/define.h {SYNTHESIS SIMULATION}
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add_file ../../../par/altera/ip/define.h {SYNTHESIS SIMULATION}
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add_file ../../../par/altera/ip/dcfifo_128_16.v {SYNTHESIS SIMULATION}
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add_file ../../../par/altera/ip/dcfifo_128b_16.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/top/ha1588.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/top/ha1588.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/reg/reg.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/reg/reg.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/rtc/rtc.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/rtc/rtc.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/tsu/tsu.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/tsu/tsu.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/tsu/ptp_parser.v {SYNTHESIS SIMULATION}
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add_file ../../../rtl/tsu/ptp_parser.v {SYNTHESIS SIMULATION}
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