| Line 37... |
Line 37... |
input [39:0] period_adj, // 39:32 ns, 31:0 ns_fraction
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input [39:0] period_adj, // 39:32 ns, 31:0 ns_fraction
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// time output: for internal with ns fraction
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// time output: for internal with ns fraction
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output [37:0] time_reg_ns, // 37:8 ns, 7:0 ns_fraction
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output [37:0] time_reg_ns, // 37:8 ns, 7:0 ns_fraction
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output [47:0] time_reg_sec, // 47:0 sec
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output [47:0] time_reg_sec, // 47:0 sec
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// time output: for external with one pps accuracy
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output reg time_one_pps,
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// time output: for external with ptp standard
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// time output: for external with ptp standard
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output [31:0] time_ptp_ns, // 31:0 ns
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output [31:0] time_ptp_ns, // 31:0 ns
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output [47:0] time_ptp_sec // 47:0 sec
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output [47:0] time_ptp_sec // 47:0 sec
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);
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);
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| Line 158... |
Line 160... |
assign time_reg_ns = time_acc_30n_08f;
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assign time_reg_ns = time_acc_30n_08f;
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assign time_reg_sec = time_acc_48s;
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assign time_reg_sec = time_acc_48s;
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// time output (48bit_s + 32bit_ns)
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// time output (48bit_s + 32bit_ns)
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assign time_ptp_ns = {2'b00, time_acc_30n_08f[37:8]};
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assign time_ptp_ns = {2'b00, time_acc_30n_08f[37:8]};
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assign time_ptp_sec = time_acc_48s;
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assign time_ptp_sec = time_acc_48s;
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// time output one pps
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always @(posedge rst or posedge clk) begin
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if (rst)
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time_one_pps <= 1'b0;
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else
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time_one_pps <= time_acc_48s_inc;
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end
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endmodule
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endmodule
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