| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : sorter_sys_tb.vhd
|
-- File : sorter_sys_tb.vhd
|
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
|
-- Author : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
|
-- Company :
|
-- Company :
|
-- Created : 2010-05-14
|
-- Created : 2010-05-14
|
-- Last update: 2011-07-06
|
-- Last update: 2018-03-21
|
-- Platform :
|
-- Platform :
|
-- Standard : VHDL'93
|
-- Standard : VHDL'93
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description:
|
-- Description:
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 113... |
Line 113... |
we <= '0';
|
we <= '0';
|
if div = 3 then
|
if div = 3 then
|
div <= 0;
|
div <= 0;
|
exit when endfile(events_in);
|
exit when endfile(events_in);
|
readline(events_in, input_line);
|
readline(events_in, input_line);
|
read(input_line, rec.init);
|
read(input_line, rec.invalid);
|
read(input_line, rec.valid);
|
|
read(input_line, skey);
|
read(input_line, skey);
|
read(input_line, spayload);
|
read(input_line, spayload);
|
rec.d_key := unsigned(skey);
|
rec.d_key := unsigned(skey);
|
rec.d_payload := spayload;
|
rec.d_payload := spayload;
|
din <= rec;
|
din <= rec;
|
| Line 127... |
Line 126... |
div <= div+1;
|
div <= div+1;
|
end if;
|
end if;
|
if dav = '1' then
|
if dav = '1' then
|
-- Process read event
|
-- Process read event
|
rec := dout;
|
rec := dout;
|
write(output_line, rec.init);
|
write(output_line, rec.invalid);
|
write(output_line, rec.valid);
|
|
write(output_line,string'(" "));
|
write(output_line,string'(" "));
|
write(output_line, std_logic_vector(rec.d_key));
|
write(output_line, std_logic_vector(rec.d_key));
|
write(output_line,string'(" "));
|
write(output_line,string'(" "));
|
write(output_line, std_logic_vector(rec.d_payload));
|
write(output_line, std_logic_vector(rec.d_payload));
|
writeline(events_out, output_line);
|
writeline(events_out, output_line);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end_sim <= true;
|
end_sim <= true;
|
rec.valid := '0';
|
rec.invalid := '0';
|
din <= rec;
|
din <= rec;
|
wait;
|
wait;
|
end process WaveGen_Proc;
|
end process WaveGen_Proc;
|
|
|
|
|
