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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity hellfire_cpu_if is
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entity hfrisc_soc is
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generic(
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generic(
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address_width: integer := 14;
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address_width: integer := 14;
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memory_file : string := "code.txt";
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memory_file : string := "code.txt";
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uart_support : string := "yes"
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uart_support : string := "yes"
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);
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);
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reset_in: in std_logic;
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reset_in: in std_logic;
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int_in: in std_logic;
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int_in: in std_logic;
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uart_read: in std_logic;
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uart_read: in std_logic;
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uart_write: out std_logic
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uart_write: out std_logic
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);
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);
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end hellfire_cpu_if;
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end hfrisc_soc;
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architecture interface of hellfire_cpu_if is
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architecture top_level of hfrisc_soc is
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signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
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signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
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signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
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signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
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signal ext_irq: std_logic_vector(7 downto 0);
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signal ext_irq: std_logic_vector(7 downto 0);
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signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
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signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
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signal ext_periph, ext_periph_dly, ready: std_logic;
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signal ext_periph, ext_periph_dly, ready: std_logic;
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signal key: std_logic_vector(127 downto 0);
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signal key: std_logic_vector(127 downto 0);
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end if;
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end if;
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end process;
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end process;
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process (data_addr_cpu, key, input, output)
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process (clock, reset, address_cpu, key, input, output)
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begin
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begin
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case data_addr_cpu(7 downto 4) is
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if reset = '1' then
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data_read_xtea <= (others => '0');
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elsif clock'event and clock = '1' then
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if (ext_periph = '1') then -- XTEA is at 0xfa000000
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case address_cpu(7 downto 4) is
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when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
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when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
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data_read_xtea <= x"000000" & "00000" & ready & control;
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data_read_xtea <= x"000000" & "00000" & ready & control;
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when "0001" => -- key[0] 0xfa000010
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when "0001" => -- key[0] 0xfa000010
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data_read_xtea <= key(127 downto 96);
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data_read_xtea <= key(127 downto 96);
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when "0010" => -- key[1] 0xfa000020
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when "0010" => -- key[1] 0xfa000020
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when "1000" => -- output[1] 0xfa000080
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when "1000" => -- output[1] 0xfa000080
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data_read_xtea <= output(31 downto 0);
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data_read_xtea <= output(31 downto 0);
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when others =>
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when others =>
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data_read_xtea <= (others => '0');
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data_read_xtea <= (others => '0');
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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process (clock, reset, data_addr_cpu, control, key, input, output)
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process (clock, reset, address_cpu, control, key, input, output)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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key <= (others => '0');
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key <= (others => '0');
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input <= (others => '0');
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input <= (others => '0');
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control <= "00";
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control <= "00";
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xfa000000
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if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xfa000000
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case data_addr_cpu(7 downto 4) is
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case address_cpu(7 downto 4) is
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when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
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when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
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control <= data_write(1 downto 0);
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control <= data_write(1 downto 0);
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when "0001" => -- key[0] 0xfa000010
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when "0001" => -- key[0] 0xfa000010
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key(127 downto 96) <= data_write;
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key(127 downto 96) <= data_write;
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when "0010" => -- key[1] 0xfa000020
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when "0010" => -- key[1] 0xfa000020
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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stall <= '0';
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stall <= '0';
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boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
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boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
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ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
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ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
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ext_periph <= '1' when address(31 downto 24) = x"fa" else '0';
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ext_periph <= '1' when address(31 downto 24) = x"fa" else '0';
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data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
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data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
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-- HF-RISC core
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-- HF-RISC core
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core: entity work.datapath
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core: entity work.datapath
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port map( clock => clock,
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port map( clock => clock,
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reset => reset,
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reset => reset,
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stall => stall_cpu,
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stall => stall_cpu,
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busy => busy_cpu,
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irq_vector => irq_vector_cpu,
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irq_vector => irq_vector_cpu,
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irq => irq_cpu,
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irq => irq_cpu,
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irq_ack => irq_ack_cpu,
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irq_ack => irq_ack_cpu,
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inst_addr => inst_addr_cpu,
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address => address_cpu,
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inst_in => inst_in_cpu,
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data_addr => data_addr_cpu,
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data_in => data_in_cpu,
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data_in => data_in_cpu,
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data_out => data_out_cpu,
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data_out => data_out_cpu,
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data_w => data_w_cpu,
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data_w => data_w_cpu,
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data_access => data_access_cpu
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data_access => data_access_cpu
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);
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);
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reset => reset,
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reset => reset,
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stall => stall,
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stall => stall,
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stall_cpu => stall_cpu,
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stall_cpu => stall_cpu,
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busy_cpu => busy_cpu,
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irq_vector_cpu => irq_vector_cpu,
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irq_vector_cpu => irq_vector_cpu,
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irq_cpu => irq_cpu,
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irq_cpu => irq_cpu,
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irq_ack_cpu => irq_ack_cpu,
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irq_ack_cpu => irq_ack_cpu,
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inst_addr_cpu => inst_addr_cpu,
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address_cpu => address_cpu,
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inst_in_cpu => inst_in_cpu,
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data_addr_cpu => data_addr_cpu,
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data_in_cpu => data_in_cpu,
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data_in_cpu => data_in_cpu,
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data_out_cpu => data_out_cpu,
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data_out_cpu => data_out_cpu,
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data_w_cpu => data_w_cpu,
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data_w_cpu => data_w_cpu,
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data_access_cpu => data_access_cpu,
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data_access_cpu => data_access_cpu,
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we_n => data_w_n_ram(3),
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we_n => data_w_n_ram(3),
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data_i => data_write(31 downto 24),
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data_i => data_write(31 downto 24),
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data_o => data_read_ram(31 downto 24)
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data_o => data_read_ram(31 downto 24)
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);
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);
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end interface;
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end top_level;
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No newline at end of file
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No newline at end of file
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