OpenCores
URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

[/] [hf-risc/] [trunk/] [hf-risc/] [platform/] [virtex4_ml403/] [virtex4ml403.vhd] - Diff between revs 13 and 18

Show entire file | Details | Blame | View Log

Rev 13 Rev 18
Line 1... Line 1...
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
 
 
entity hellfire_cpu_if is
entity hfrisc_soc is
        generic(
        generic(
                address_width: integer := 16;
                address_width: integer := 16;
                memory_file : string := "code.txt";
                memory_file : string := "code.txt";
                uart_support : string := "yes"
                uart_support : string := "yes"
        );
        );
        port (  clk_in:         in std_logic;
        port (  clk_in:         in std_logic;
                reset_in:       in std_logic;
                reset_in:       in std_logic;
                uart_read:      in std_logic;
                uart_read:      in std_logic;
                uart_write:     out std_logic
                uart_write:     out std_logic
        );
        );
end hellfire_cpu_if;
end hfrisc_soc;
 
 
architecture interface of hellfire_cpu_if is
architecture top_level of hfrisc_soc is
        signal clock, reset, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly: std_logic;
        signal clock, reset, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, rff1, ram_dly: std_logic;
        signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
        signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
        signal ext_irq: std_logic_vector(7 downto 0);
        signal ext_irq: std_logic_vector(7 downto 0);
        signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
        signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
begin
begin
        reset <= not reset_in;
 
 
 
        -- clock divider (50MHz clock from 100MHz main clock for ML403 kit)
        -- clock divider (50MHz clock from 100MHz main clock for ML403 kit)
        process (reset, clk_in, clock)
        process (reset, clk_in, clock)
        begin
        begin
                if reset = '1' then
                if reset = '1' then
                        clock <= '0';
                        clock <= '0';
Line 67... Line 65...
        -- HF-RISC core
        -- HF-RISC core
        core: entity work.datapath
        core: entity work.datapath
        port map(       clock => clock,
        port map(       clock => clock,
                        reset => reset,
                        reset => reset,
                        stall => stall_cpu,
                        stall => stall_cpu,
                        busy => busy_cpu,
 
                        irq_vector => irq_vector_cpu,
                        irq_vector => irq_vector_cpu,
                        irq => irq_cpu,
                        irq => irq_cpu,
                        irq_ack => irq_ack_cpu,
                        irq_ack => irq_ack_cpu,
                        inst_addr => inst_addr_cpu,
                        address => address_cpu,
                        inst_in => inst_in_cpu,
 
                        data_addr => data_addr_cpu,
 
                        data_in => data_in_cpu,
                        data_in => data_in_cpu,
                        data_out => data_out_cpu,
                        data_out => data_out_cpu,
                        data_w => data_w_cpu,
                        data_w => data_w_cpu,
                        data_access => data_access_cpu
                        data_access => data_access_cpu
        );
        );
Line 92... Line 87...
                reset => reset,
                reset => reset,
 
 
                stall => stall,
                stall => stall,
 
 
                stall_cpu => stall_cpu,
                stall_cpu => stall_cpu,
                busy_cpu => busy_cpu,
 
                irq_vector_cpu => irq_vector_cpu,
                irq_vector_cpu => irq_vector_cpu,
                irq_cpu => irq_cpu,
                irq_cpu => irq_cpu,
                irq_ack_cpu => irq_ack_cpu,
                irq_ack_cpu => irq_ack_cpu,
                inst_addr_cpu => inst_addr_cpu,
                address_cpu => address_cpu,
                inst_in_cpu => inst_in_cpu,
 
                data_addr_cpu => data_addr_cpu,
 
                data_in_cpu => data_in_cpu,
                data_in_cpu => data_in_cpu,
                data_out_cpu => data_out_cpu,
                data_out_cpu => data_out_cpu,
                data_w_cpu => data_w_cpu,
                data_w_cpu => data_w_cpu,
                data_access_cpu => data_access_cpu,
                data_access_cpu => data_access_cpu,
 
 
Line 183... Line 175...
                we_n    => data_w_n_ram(3),
                we_n    => data_w_n_ram(3),
                data_i  => data_write(31 downto 24),
                data_i  => data_write(31 downto 24),
                data_o  => data_read_ram(31 downto 24)
                data_o  => data_read_ram(31 downto 24)
        );
        );
 
 
end interface;
end top_level;
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.