| Line 30... |
Line 30... |
signal data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
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signal data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
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signal opcode, funct: std_logic_vector(5 downto 0);
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signal opcode, funct: std_logic_vector(5 downto 0);
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signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);
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signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal imm: std_logic_vector(15 downto 0);
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signal imm: std_logic_vector(15 downto 0);
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signal wreg, zero, less_than, br_link_ctl, branch_taken, branch_taken_dly, jump_taken, jump_taken_dly, stall_reg: std_logic;
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signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, stall_reg: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
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-- control signals
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-- control signals
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signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
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signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
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signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
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signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
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| Line 65... |
Line 65... |
if stall = '0' then
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if stall = '0' then
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if busy = '0' then
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if busy = '0' then
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pc <= pc_next;
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pc <= pc_next;
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pc_last <= pc;
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pc_last <= pc;
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else
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else
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if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and branch_taken_dly = '0' and jump_taken_dly = '0' then
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if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and bds = '0' then
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pc <= pc_last;
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pc <= pc_last;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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| Line 92... |
Line 92... |
process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, busy, stall)
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process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, busy, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_ack_s_dly <= '0';
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irq_ack_s_dly <= '0';
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bds <= '0';
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bds <= '0';
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branch_taken_dly <= '0';
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jump_taken_dly <= '0';
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mem_to_reg_ctl_dly <= '0';
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mem_to_reg_ctl_dly <= '0';
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stall_reg <= '0';
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stall_reg <= '0';
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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stall_reg <= stall;
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stall_reg <= stall;
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if stall = '0' then
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if stall = '0' then
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| Line 107... |
Line 105... |
if branch_taken = '1' or jump_taken = '1' then
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if branch_taken = '1' or jump_taken = '1' then
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bds <= '1';
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bds <= '1';
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else
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else
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bds <= '0';
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bds <= '0';
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end if;
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end if;
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branch_taken_dly <= branch_taken;
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jump_taken_dly <= jump_taken;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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| Line 192... |
Line 188... |
mem_read_ctl_r <= "00";
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mem_read_ctl_r <= "00";
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signed_rd_ctl_r <= '0';
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signed_rd_ctl_r <= '0';
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shift_ctl_r <= '0';
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shift_ctl_r <= '0';
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else
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else
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if busy = '0' then
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if busy = '0' then
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if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or branch_taken_dly = '1' or jump_taken_dly = '1' then
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if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or bds = '1' then
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rs_r <= (others => '0');
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rs_r <= (others => '0');
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rt_r <= (others => '0');
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rt_r <= (others => '0');
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rd_r <= (others => '0');
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rd_r <= (others => '0');
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imm_r <= (others => '0');
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imm_r <= (others => '0');
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reg_dst_ctl_r <= '0';
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reg_dst_ctl_r <= '0';
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